ST16C550CQ48 EXAR [Exar Corporation], ST16C550CQ48 Datasheet - Page 13

• Manufacturer Part Number: ST16C550CQ48
• Manufacturer: EXAR [Exar Corporation]

REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1.
Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.
Rev. 4.30
Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1. Note 1*
A2 A1 A0
0
0
0
0
0
0
1
1
1
1
0
0
Table 4, ST16C550 INTERNAL REGISTERS
General Register Set
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
RHR [XX]
MSR [X0]
THR [XX]
MCR [00]
SPR [FF]
DLM [XX]
Register
[Default]
FCR [00]
LCR [00]
DLL [XX]
LSR [60]
Note *2
IER [00]
ISR [01]
enabled
FIFO’s
RCVR
trigger
(MSB)
divisor
enable
BIT-7
bit-15
FIFO
latch
error
bit-7
bit-7
bit-7
data
bit-7
CD
0
0
enabled
FIFO’s
RCVR
trigger
BIT-6
(LSB)
trans.
empty
bit-14
break
bit-6
bit-6
bit-6
bit-6
set
RI
0
0
holding
empty
BIT-5
trans.
bit-13
parity
DSR
bit-5
bit-5
bit-5
bit-5
set
0
0
0
0
13
loopback
interrupt
enable
BIT-4
bit-12
parity
break
even
CTS
bit-4
bit-4
bit-4
bit-4
0
0
0
interrupt
modem
framing
enable
priority
status
select
BIT-3
bit-11
mode
parity
DMA
-OP2
error
delta
bit-3
bit-3
bit-2
bit-3
bit-3
-CD
INT
interrupt
receive
priority
status
BIT-2
XMIT
bit-10
FIFO
-OP1
parity
reset
error
delta
bit-2
bit-2
bit-1
bit-2
bit-2
stop
INT
line
bits
-RI
ST16C550
transmit
register
overrun
holding
RCVR
priority
length
BIT-1
-DSR
FIFO
-RTS
reset
word
error
delta
bit-1
bit-1
bit-1
bit-0
bit-1
bit-1
bit-9
INT
register
receive
holding
receive
enable
length
BIT-0
status
ready
-CTS
FIFO
-DTR
word
delta
bit-0
bit-0
bit-0
bit-0
data
bit-0
bit-8
INT