sp5524 Zarlink Semiconductor, sp5524 Datasheet - Page 6

• Manufacturer Part Number: sp5524
• Description: Bidirectional I2c Bus Controlled Synthesiser
• Manufacturer: Zarlink Semiconductor

Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
Address
Status byte
A2
1
0
0
0
0
A1
0
1
1
0
0
A
MA1, MA0
CP
T1
T0
OS
P7, P6
P3, P2, P1, P0
POR
FL
I2, I1, I0
A2, A1, A0
X
Table 3 ADC levels
A0
0
1
0
1
0
Voltage input to P1
0·45V
0·3V
0·15V
Table 1 Write data format (MSB transmitted first)
0·6V
0V to 0·15V
CC
CC
CC
CC
to 0·45V
: Acknowledge bit
: Variable address bits (see Table 4)
: Charge Pump current select
: Test mode selection
: Charge pump disable
: Varactor drive Output disable Switch
: Control output port states
: Power On Reset indicator
: Phase lock detect flag
: Digital information from ports P0, P2 and P3 respectively
: 5-level ADC data from P1 (see Table 3)
: Don't care
to 13·2V
to 0·6V
to 0·3V
POR
MSB
P7
2
1
1
0
1
7
Table 2 Read data format
CC
Fig. 3 Data formats
CC
CC
CC
2
CP
P6
FL
2
1
1
14
6
2
T1
2
I2
X
0
0
13
5
2
T0
2
I1
0
X
0
12
4
2
P3
2
I0
0
1
0
11
3
MA1
MA1
MA1
2
P2
A2
2
1
0
0
1
1
10
2
Table 4 Address selection
MA0
MA0
MA0
P1
A1
2
2
1
0
1
0
1
9
1
LSB
Voltage input to P7
OS
P0
A0
2
2
0·3V
0
1
0·8V
8
0
0V to 0·2V
Always valid
CC
CC
A
A
A
A
A
A
A
to 0·7V
to 13·2V
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
CC
CC
SP5524
5