ml6692 Microsemi Corporation, ml6692 Datasheet - Page 16

• Manufacturer Part Number: ml6692
• Description: 100base-tx Physical Layer With
• Manufacturer: Microsemi Corporation

ML6692
MII MANAGEMENT INTERFACE REGISTERS
16
1.10 – 1.6 Not Used
4.12-4.10 Reserved
4.4-4.1
BIT(S)
BIT(S)
1.15
1.14
1.13
1.12
1.11
4.15
4.14
4.13
1.5
1.4
1.3
1.2
1.1
1.0
4.9
4.8
4.7
4.6
4.5
4.0
100BASE-T4
100BASE-TX full duplex
100BASE-TX half duplex
10Mb/s full duplex
10BASE-T (half duplex)
Auto negotiation compl.
Not Used
Auto negotiation ability
Link status
Not Used
Extended capability
Next Page
Reserved
Remote fault
100BASE-T4 capability
100BASE-TX full duplex
100BASE-TX
10BASE-T full duplex
10BASE-T
Selector field
Selector field
NAME
NAME
1 = extended register capabilities
All these bits are 0 for 802.3 LANs
This bit is a 1 for 802.3 LANs
1 = 100BASE-T4 capability
0 = no 100BASE-T4 capability
1 = full duplex 100BASE-TX capability
0 = No full duplex 100BASE-TX capability
1 = half duplex 100BASE-TX capability
0 = no half duplex 100BASE-TX capability
1 = full duplex 10Mb/s capability
0 = No full duplex 10Mb/s capability
1 = 10BASE-T (half duplex) capability
0 = No 10BASE-T (half duplex) capability
1 = auto negotiation process complete
0 = auto negotiation not complete
1 = auto negotiation capability available
0 = auto negotiation capability not available
1 = one and only one PHY-specific link is up
0 = link is down
0 = basic register set only
1 = additional link code word pages
0 = no additional pages
Write as zero, ignore on read
1 = remote wire fault detected
0 = no remote wire fault detected
(Not used at present)
1 = 100BASE-T4 capability
0 = no 100BASE-T4 capability
1 = 100BASE-TX full duplex capability
0 = no 100BASE-Tfull duplex
1 = 100BASE-TX capability
0 = no 100BASE-TX capability
1 = 10BASE-T full duplex capability
0 = no 10BASE-T full duplex capability
1 = 10BASE-T capability
0 = no 10BASE-T capability
Table 4. Advertisement Register
Table 3. Status Register
DESCRIPTION
DESCRIPTION
(Continuied)
RO/LL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
10HDUP (Bit I.10)
10HDUP (Bit I.10)
link fail until read
10FDUP (Bit I.9)
10FDUP (Bit I.9)
latch low after
100T4 (bit I.8)
100T4 (Bit I.8)
DEFAULT
DEFAULT
1
1
0
1
1
0
0
1
1
0
1