lxt351 Intel Corporation, lxt351 Datasheet
lxt351
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lxt351 Summary of contents
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation The LXT351 is a full-featured, fully-integrated transceiver for T1 and E1 short-haul applications. The LXT351 is software switchable between T1 and E1 operation, and offers pulse equalization settings for all short-haul T1 and E1 line interface (LIU) applications. The LXT351 offers an Intel/Motorola compatible parallel port for microprocessor control. The device incorporates advanced crystal-less digital jitter attenuation in either the transmit or receive data path starting ...
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... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT351 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Contents 1.0 Pin Assignments and Signal Descriptions 1.1 Mode Dependent Signals ...................................................................................... 9 2.0 Functional Description 2.1 Initialization..........................................................................................................13 2.1.1 Reset Operation .....................................................................................13 2.2 Transmitter ..........................................................................................................13 2.2.1 Transmit Digital Data Interface...............................................................13 2.2.2 Transmit Monitoring................................................................................14 2.2.3 Transmit Drivers .....................................................................................14 2.2.4 Transmit Idle Mode.................................................................................14 2.2.5 Transmit Pulse Shape ............................................................................14 2.3 Receiver ..............................................................................................................15 2.3.1 Receive Data Recovery..........................................................................15 2 ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation 5.0 Test Specifications 6.0 Mechanical Specifications Figures 1 LXT351 Block Diagram ......................................................................................... 7 2 LXT351 Pin Assignments...................................................................................... 8 3 50% Duty Cycle Coding ...................................................................................... 14 4 Local Loopback ................................................................................................... 16 5 TAOS with LLOOP .............................................................................................. 17 6 Analog Loopback ................................................................................................ 18 7 Remote Loopback ............................................................................................... 19 8 Dual Loopback .................................................................................................... 19 9 TAOS Data Path ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Tables 1 LXT351 Clock and Data Pin Assignments by Mode1............................................ 9 2 LXT351 Processor Interface Pins.......................................................................... 9 3 LXT351 Signal Descriptions ................................................................................10 4 Diagnostic Mode Summary .................................................................................16 5 Register Addresses .............................................................................................24 6 Register and Bit Summary ..................................................................................24 7 Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................25 8 Equalizer Control Input Settings ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Revision History Revision Date 6 Description Datasheet ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Figure 1. LXT351 Block Diagram Datasheet 7 ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT351 Pin Assignments RNEG / BPV RPOS / RDATA ALE / AS RNEG / BPV RPOS / RDATA ALE / LXT351PE XX LXT351PE RCLK 8 XXXXXX XXXXXXXX ...
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... INT 23 31 AD0 24 32 AD1 Datasheet 2, the LXT351 has several pins that change function (and signal name) Table 1 and Table 2. LXT351 signals are described in Unipolar Mode MCLK TCLK TDATA INSBPV BPV RDATA RCLK TTIP TRING RTIP RRING ...
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... Transmit Insert Logic Error. In QRSS mode, a Low-to-High transition on INSLER inserts a logic error into the transmitted QRSS data pattern. The DI error follows the data flow of the active loopback mode. The LXT351 samples this pin on the falling edge of TCLK (or MCLK, if TCLK is not present). ...
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... Address/Data Bus 6 and 7. Used with AD0 - AD5 to form the address/ DI/O data bus. Conforms to Intel and Motorola multiplexed address/data bus specifications. Write Intel bus, driving WR Low commands a LXT351 register write operation. DI Read/Write Motorola bus, driving R/W High commands a LXT351 register read operation; driving it Low commands a write operation. ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Table 3. LXT351 Signal Descriptions (Continued) Pin # Symbol PLCC QFP 22 29 GND 23 31 AD0 24 32 AD1 25 35 AD2 26 36 AD3 27 37 AD4 28 38 AD5 8, 11, 12, 14, 17, 22, - 23, 26, n/c 28, 30, 33, 34, 40 Digital Input Digital Output; DI/O = Digital Input/Output Analog Input Analog Output. ...
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... It interfaces with two twisted-pair lines (one pair each for transmit and receive) through standard pulse transformers and appropriate resistors. The figure on the front page of this data sheet shows a block diagram of the LXT351. Control of the chip is via the 8-bit parallel microprocessor port. Stand-alone operation is not supported. ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation 2.2.2 Transmit Monitoring The transmitter includes a short circuit limiter that limits the current sourced into a low impedance load. The limiter automatically resets when the load current drops below the limit. The current is determined by the interface circuitry (total resistance on transmit side). ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 2.3 Receiver A 1:1 transformer provides the interface to the twisted-pair line. Recovered data is output at RPOS/ RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK. Refer to and Table 28 on page 38 2.3.1 Receive Data Recovery The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal ...
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... JAL enabled active in the loopback circuit bypassed not active in the loopback circuit. The transmitter circuits are unaffected by LLOOP. LXT351 transmits the TPOS/TNEG or TDATA inputs (or a stream TAOS is asserted) normally. When used in this mode, the transceiver can function as a stand-alone jitter attenuator ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Table 4. Diagnostic Mode Summary Diagnostic Mode Internal Data Pattern Generation Transmit All Ones (TAOS) Quasi-Random Signal Source (QRSS) Error Insertion and Detection Bipolar Violation Insertion (INSBPV) Logic Error Insertion (INSLER) Bipolar Violation Detection (BPV) ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation 2.5.1.2 Analog Loopback See Figure 6. Analog loopback (ALOOP) exercises the maximum number of functional blocks. ALOOP operation disconnects the RTIP/RRING inputs from the line and routes the transmit outputs back into the receive inputs. This tests the encoders/decoders, jitter attenuator, transmitter, receiver and timing recovery sections ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Figure 7. Remote Loopback 2.5.1.4 Dual Loopback See Figure 8. To select Dual loopback (DLOOP) set bits CR2.ERLOOP and CR2.ELLOOP DLOOP mode, the transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the Jitter Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA ...
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... The TQRSS bit in the Transition Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear command. The LXT351 can generate an interrupt to indicate that QRSS detection has occurred, or that synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0. 20 ...
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... If LLOOP and TAOS are both active, the BPV is looped back to RNEG/BPV indicator and the line driver transmits all ones with no violation • BPV insertion is disabled with RLOOP active With the LXT351 configured to transmit internally generated data patterns, a BPV can be inserted into the transmit pattern regardless of whether the device is in the Unipolar or Bipolar mode of operation. 2.5.3.2 ...
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... Loss of Signal The LXT351 Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI 300233. The receiver LOS monitor loads a digital counter at the RCLK frequency. The count increments with each received 0 and the counter resets receipt When the count reaches “ ...
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... Interrupt Handling The LXT351 provides a latched interrupt output pin (INT). When enabled, a change in any of the Performance Status Register bits will generate an interrupt. An interrupt can also be generated when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an interrupt occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has internal pull-down only ...
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... The LXT351 contains five read/write and two read-only registers that are accessible via the parallel port. Table 5 lists the LXT351 register addresses. Only bits A6 through A1 of the address byte are valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/write (R/W) bit. Table 6 identifies the name of each register bit ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Table 7. Control Register #1 Read/Write, Address (A7-A0) = x010000x Bit Name 0 EC1 Sets mode (T1 or E1) and equalizer 1 EC2 (see Table 8 2 EC3 3 - Reserved, set this bit to 0, ignore when reading Enable Unipolar I/O mode and allow insertion/detection of BPVs. ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Table 9. Control Register #2 Read/Write, Address (A7-A0) = x010001x Bit Name 1 = Enable Transmit All Ones 4 ETAOS 0 = Disable Transmit All Ones 5 EPAT0 Selects internal data pattern transmission. See right hand section of table for codes. 6 EPAT1 1 = Reset device states and clear all registers. ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x Bit Name 1 = Clear/Mask Driver Failure Monitor Open interrupt. 5 CDFMO 0 = Enable Driver Failure Monitor Open interrupt Clear/Mask Elastic Store Overflow interrupt. 6 CESO 0 = Enable Elastic Store Overflow interrupt. ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x Bit Name 1 = Driver Failure Monitor Open detected. 5 DFMO 0 = Driver Failure Monitor Open not detected Built-In Self Test passed. 6 BIST 0 = Built-In Self Test did not pass (or was not run). ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 4.0 Application Information 4.1 Transmit Return Loss Table 15 shows the specification for transmit return loss in E1 applications. The G.703/CH PTT specification is a Swiss Telecommunications Ministry specification. Table 16 and Table 17 4.2 Transformer Data Specifications for transformers are listed in with the LXT351 are specified in 4 ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Table 16. Transmit Return Loss (2.048 Mbps) EC3-1 Xfrmr/Rt 1:2/ 9.1 000 1:2.3/9.1 Table 17. Transmit Return Loss (1.544 Mbps) EC3-1 Xfrmr/Rt 1:2/ 9.1 2 011 1 1:1.15 0 1:1.15 transmit transformer keeps the total transceiver power dissipation at a low level blocking capacitor must be placed on TTIP or TRING ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Table 19. Recommended Transformers Tx/Rx Turns Ratio 1:1.15 Tx 1:2 1:2.3 Rx 1:1 4.4.1 LXT351 Application Circuit Figure 11 shows a typical application using the LXT351. See transformers (T1 and T2), resistors (Rt and R Note: If the application includes surge protection, such as a varistor or sidactor on the TTIP/TRING lines, ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Figure 11. Typical T1/E1 LXT351 Application 2.048 MHz/ 1.544 MHz TCLK TPOS T1/E1 TNEG Framer RCLK RPOS RNEG 68 F 0.1 F NOTES: 1. See 100 120 MCLK TCLK TPOS TNEG RCLK LXT351 RPOS RNEG ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 5.0 Test Specifications Note: Table 20 through Table 31 specifications of the LXT350/351 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in recommended operating conditions specified in Table 20. Absolute Maximum Ratings Parameter ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Table 22. DC Electrical Characteristics Parameter Digital I/O pins 2 High level input voltage (pins 1-5, 9-12, 17, 23-28) 2 Low level input voltage (pins 1-5, 9-12, 17, 23-28) 2 High level output voltage (pins 6-8, 10, 11,23, 28) 2 Low level output voltage (pins 6-8, 10, 11,23, 28) Input leakage current 1. Typical figures are at 25° ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Figure 12. 2.048 Mbps E1 Pulse (See Table 24 100% 50% 0% Table 24. 2.048 Mbps E1 Pulse Mask Specifications Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Figure 13. 1.544 Mbps T1 Pulse, DSX-1 (See Table 25) 1.5 Normalized Amplitude 1.0 0.5 -0.5 0.0 -0.5 0 Table 25. 1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications Minimum Curve Time (UI) -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 36 0.5 Time (in Unit Intervals) DSX-1 Template (per ANSI T1. 102-1993) Amplitude Time (UI) -0 ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Table 26. Master and Transmit Clock Timing Characteristics for T1 Operation (See Figure 14) Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Table 28. Receive Timing Characteristics for T1 Operation (See Figure 15) Parameter 2, 3 Receive clock duty cycle 2, 3 Receive clock pulse width Receive clock pulse width High 1,3 Receive clock pulse width Low RPOS/RNEG to RCLK rise time RCLK rise to RPOS/RNEG hold time 1. Typical s are at 25 ° ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Table 30. 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16) Parameter ALE pulse width Address valid to ALE falling edge ALE falling edge to address hold time ALE falling edge to RD falling edge ALE falling edge to WR falling edge ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Figure 16. Intel Address/Data Bus Timing 0ns 50ns CS T LHLL T LLAX ALE T AVLL RD AD0-7_R WR AD0-7_W Table 31. 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 17) Parameter DS rising edge to AS rising edge AS High pulse width ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Figure 17. Motorola Address/Data Bus Timing CS T ASHASL T AVASL AS DS R/W_Read AD0-7_Read R/W_Write AD0-7_Write Figure 18. Typical T1 Jitter Tolerance 1000 UI 500 UI Jitter @ 10 Hz 138 UI 100 0 Datasheet ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Figure 19. Typical E1 Jitter Tolerance Datasheet ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 Figure 20. Typical E1 Jitter Attenuation Datasheet 43 ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Figure 21. Typical T1 Jitter Attenuation 44 Datasheet ...
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... T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351 6.0 Mechanical Specifications Figure 22. Plastic Leaded Chip Carrier Package Specifications 28-Pin PLCC • Part Number LXT351PE • Extended Temperature Range (-40 ° ° Dim BSC—Basic Spacing between Centers. ...
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... LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation Figure 23. Plastic Quad Flat Package Specifications 44-Pin PQFP • • Dim BSC—Basic Spacing between Centers. 46 Part Number LXT351QE Extended Temperature Range (-40 ° °C) ...