lxt384 Intel Corporation, lxt384 Datasheet - Page 35

• Manufacturer Part Number: lxt384
• Description: Octal T1/e1/j1 Short Haul Transceiver
• Manufacturer: Intel Corporation

5.5
Document Number: 248994
Revision Number: 004
Revision Date: September 22, 2005
Table 11. Clocks and Clock-Related Signals (Sheet 1 of 2)
Note: Within this table, ‘RCLK’ references RCLK7:0 and ‘TCLK’ references TCLK7:0. Each RCLK
Clocks and Clock-Related Signals
Table 11
and TCLK signal is used with corresponding signals.
CLKE
•
•
1. DI: Digital Input
Signal
Name
Example: RCLK6 is the receive clock used by RPOS6 and RNEG6.
Example: TCLK5 is the transmit clock used by TPOS5 and TNEG5.
lists and describes LXT384 Transceiver clocks and clock-related signals.
QFP
Pin
115
PBGA
Ball
E13
Signal
Type
DI
Clock Edge Select Input.
CLKE is used in clock and data recovery. When the recovery mode is
for:
Intel
• Clock recovery (see
• Data recovery (see
the CLKE pin:
• Low causes (1) both RDATA or RPOS and RNEG to be valid on
• High causes (1) both RDATA or RPOS and RNEG to be valid on
Mode”), the output polarity on both RDATA or RPOS and RNEG
is:
• Active-low when CLKE is low.
• Active-high when CLKE is high
®
the rising edge of RCLK and (2) SDO to be valid on the falling
edge of SCLK. (See
Transceiver - Transmit
the falling edge of RCLK and (2) SDO to be valid on the rising
edge of SCLK. (See
Transceiver - Transmit
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
CLKE
High
Low
RCLK for Valid
RCLK
RCLK
RNEG/RPOS
Section 6.3.4, “Receiver Data Recovery
Section 6.3.1, “Receiver
Signal Description
Figure 20
Figure 20
Timing”.)
Timing”.)
SCLK for Valid
in
in
SCLK
SCLK
Section 19, “Intel
Section 19, “Intel
SDO
Clocking”), setting
®
®
LXT384
LXT384
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