cxa3003r Sony Electronics, cxa3003r Datasheet - Page 25

• Manufacturer Part Number: cxa3003r
• Description: Baseband Analog Processing Ic For Dual-mode Cdma/fm Cellular Phone
• Manufacturer: Sony Electronics

9. FM Transmit Signal Path
10.Operating Modes
11.House Keeping ADC
An analog FM modulation signal is constructed from 8-bit digital data supplied by the digital processing
section. Only the Q-channel DAC is used in this IC in FM mode, all other CDMA circuits are disabled.
The DAC output is filtered by a low-pass anti-aliasing filter. The filtered DAC output is the analog FM
modulation signal, FM MOD. This signal modulates the frequency of this IC transmit VCO using external
components when in FM RXTX Mode.
This IC has several modes of operation. The CDMA RXTX or FM RXTX modes are in effect when the
telephone is making a call. IDLE mode is in effect when no call is in progress but the telephone receiver
is active (ready to answer a call). SLEEP mode is a low-power mode in which the telephone cannot
receive a call.
This IC operating modes are defined by the states of three digital inputs: FMB, IDLEB, and SLEEPB. The
power consumed by this IC is minimized by controlling these logic signals and disabling unused circuits.
The selected circuits in this IC become active after the states of the operating mode controls are changed.
The House Keeping ADC provides DC measurement capability to the telephone. It is a low speed, 8-bit
resolution, successive approximation analog-to-digital converter. It is designed to digitize DC voltages
applied to the ADCIN pin from battery level, temperature, and other low frequency control or monitoring
sensors.
This ADC is in a power-down state during normal operation. It is activated by a positive-going pulse on
ADCENBL. When this input is driven high, the House Keeping ADC powers up, samples and holds the
voltage applied to ADCIN, and begins a conversion. The ADC output is available from a serial digital
interface. Each of the eight data bits is valid (MSB first) during the rising edge of the ADCCLK output. A
rising edge of ADCENBL during a conversion will be ignored. ADCENBL must be low and a conversion
completed before a new conversion can be started.
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CXA3003R