74F632QC NSC [National Semiconductor], 74F632QC Datasheet - Page 3

• Manufacturer Part Number: 74F632QC
• Description: 32-Bit Parallel Error Detection and Correction Circuit
• Manufacturer: NSC [National Semiconductor]

Memory
Write
Connection Diagram
Cycle
See Table II for details of check bit generation
Order Number DP8406D (74F632DC)
Generate
Check Word
Function
See NS Package Number D52A
EDAC
Pin Assignment for
Side Brazed DIP
S
L
Control
1
(Continued)
S
L
0
Data I O
Input
TABLE I Write Control Function
TL F 9579 – 2
DB Control
OEB
H
n
3
Functional Description
MEMORY WRITE CYCLE DETAILS
During a memory write cycle the check bits (CB
CB
put parity generators using the 32-bit data word as defined
in Table II These seven check bits are stored in memory
along with the original 32-bit data word This 32-bit word will
later be used in the memory read cycle for error detection
and correction
ERROR DETECTION AND CORRECTION DETAILS
During a memory read cycle the 7-bit check word is re-
trieved along with the actual data In order to be able to
determine whether the data from memory is acceptable to
use as presented to the bus the error flags must be tested
to determine if they are at the HIGH level
The first case in Table III represents the normal no-error
conditions The EDAC presents HIGHs on both flags The
next two cases of single-bit errors give a HIGH on MERR
and a LOW on ERR which is the signal for a correctable
error and the EDAC should be sent through the correction
cycle The last three cases of double-bit errors will cause
the EDAC to signal LOWs on both ERR and MERR which is
the interrupt indication for the CPU
Error detection is accomplished as the 7-bit check word and
the 32-bit data word from memory are applied to internal
parity generators checkers If the parity of all seven group-
ings of data and check bits is correct it is assumed that no
error has occurred and both error flags will be HIGH
6
DB Output
) are generated internally in the EDAC by seven 16-in-
LEDBO
Latch
X
Check I O
Output
Check Bit
Control
OECB
CB
L
ERR
Error Flags
H
0
through
MERR
H