ls7030 LSI Computer Systems, Inc., ls7030 Datasheet

ls7030

Manufacturer Part Number

ls7030

Description

8 Decade Multiplexed Counter

Manufacturer

LSI Computer Systems, Inc.

Datasheet

1.LS7030.pdf (4 pages)

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7030 - 012703 - 1

FEATURES:

• DC to 7.5 MHz Count Frequency

• Multiplexed BCD and 7 Segment Outputs

• DC to 500 kHz Scan Frequency

• +4.75V to +15V Operation (V

• Compatible with CMOS Logic

• High Input Noise Immunity

• Counter Output Latches

• Leading Zero Blanking

• Low Power Dissipation

• All inputs protected

• 40 Pin DIP - See Figure 1

DESCRIPTION: (See Block Diagram, Figure 4.)

The LS7030 is a MOS, 8 decade up counter. The circuit includes

latches, multiplexer, leading zero blanking and 7 segment data

outputs.

8 DECADE UP COUNTER

The eight decade ripple through counter increments on the neg-

ative edge of the input count pulse. Maximum ripple time is 12µs

(99999999 to 00000000). Maximum count frequency is 7.5MHz.

RESET

All decades are reset to zero when Reset input is brought low for

a minimum of 4µs. The Overflow flip-flop is reset at the same

time. Reset must be high for a minimum of 1µs before next valid

count can be recorded.

LATCHES

Contents of counter are transferred to latches when LOAD signal

is brought low for a minimum of 4µs and kept low until a minimum

of 12µs has elapsed from previous negative edge of count pulse

(ripple time). Storage of valid data occurs when LOAD signal is

high for a minimum of 1µs before next negative edge of count

pulse or reset. Data is transferred for Overflow flip-flop to Over-

flow latch at the same time.

SCAN OSCILLATOR AND COUNTER

The scan counter is driven by an internal oscillator whose fre-

quency is determined by a capacitor connected between Os-

cillator input and Scan input. An external scan clock applied to

Scan input can also drive the scan counter. Scan counter ad-

vances on negative edge of scan clock.

The counter scans from MSD to LSD. When Scan Reset input is

brought high the scan counter is forced to MSD state. Internal

synchonization guarantees proper scanning no matter when Scan

Reset is brought low relative to scan clock. Maximum scan

frequency is 500kHz.

DECIMAL POINT

A high at the Decimal Point input resets the Blanking flip-flop

causing the display to unblank. Decimal Point should be brought

high at start of digit time which has active Decimal Point.

U L

A3800

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

8 DECADE MULTIPLEXED COUNTER

- V

)

DIGIT

S T R O B E

O U T P U T S

DECADE 6 OUTPUT,

DECADE 7 OUTPUT,

DECADE 6 OUTPUT,

DIGIT STROBES

Timing of Digit Strobes is arranged such that both edges of strobe

are guardbanded by a minimum 400ns within valid BCD data when

scan frequency is 100kHz or less. The guardband is a minimum of

200ns at 250kHz scan frequency. At 500kHz only negative edge of

Strobe is guaranteed to be within valid BCD data by a minimum

200ns.

OVERFLOW

The Overflow flip-flop sets on the first negative transition of the Over-

flow Input and remains set until Reset is brought low. Data is trans-

ferred from Overflow flip-flop to Overflow Latch when Load is brought

low. A high at the Overflow Latch causes display to unblank. Over-

flow Output is output of Overflow Latch. MSB outputs of Decades

6, 7, 8 are available for use as Overflow Input.

BLANKING

Leading zero blanking is employed. At start of each MSD to LSD

scan, display is blanked until a nonzero digit or active decimal point is

encountered. Displaly unblanks during LSD time and for a whole

scan when Overflow output is high. When Scan Reset is applied, dis-

play blanks to prevent display damage.

Blanking information is available at Blank output and is incorporated

into 7 segment information.

DECIMAL POINT INPUT

OVERFLOW OUTPUT

SCAN RESET INPUT

BCD

DATA

O U T P U T S

OVERFLOW INPUT

BLANK OUTPUT

MSD STROBE 8

LSD STROBE 1

S T R O B E 7

S T R O B E 6

S T R O B E 5

S T R O B E 4

S T R O B E 3

S T R O B E 2

CONNECTION DIAGRAM - TOP VIEW

(631) 271-0400 FAX (631) 271-0405

LS7030

L S 7 0 3 0

FIGURE 1

TEST COUNT INPUT, DIGITS 3 - 8

OSC. INPUT

SCAN INPUT

LAMP TEST INPUT

N.C.

COUNT INPUT

N.C.

RESET COUNTER INPUT

LOAD LATCH INPUT

SEGMENT

O U T P U T S

SEGMENT

O U T P U T S

January 2003

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ls7030 Summary of contents

Page 1

... Low Power Dissipation • All inputs protected • 40 Pin DIP - See Figure 1 DESCRIPTION: (See Block Diagram, Figure 4.) The LS7030 is a MOS, 8 decade up counter. The circuit includes latches, multiplexer, leading zero blanking and 7 segment data outputs. 8 DECADE UP COUNTER The eight decade ripple through counter increments on the neg- ative edge of the input count pulse. Maximum ripple time is 12µ ...

Page 2

BCD and 7 SEGMENT DATA Data is available in BCD and 7 segment format. BCD data can be demultiplexed using Digit Strobes as latch enable signals. POWER SUPPLIES +4.75 Volts to +15 Volts single power supply operation is obtained when ...

Page 3

ELECTRICAL CHARACTERISTICS OV, Vss = +4.75 to +15V, -25˚ PARAMETER Count test and Count frequency (Vss = +5V ± 5%) (Vss = +10V) (Vss = +15V) Scan frequency Count Pulse Width (Vss = +5V ...

Page 4

... LATCH LATCH LATCH BCD C BCD C BCD C COUNTER COUNTER COUNTER FIGURE 4. LS7030 BLOCK DIAGRAM DECIMAL POINT INPUT 10 BLANKING F MUX MUX MUX ...

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