cxd1217q Sony Electronics, cxd1217q Datasheet - Page 6

no-image

cxd1217q

Manufacturer Part Number
cxd1217q
Description
Synchronizing Signal Generator For Video Camera
Manufacturer
Sony Electronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CXD1217Q
Manufacturer:
SONY
Quantity:
3 107
Part Number:
CXD1217Q
Manufacturer:
SONY/索尼
Quantity:
20 000
• V reset (VRI input)
• LALT reset (LALTRI input)
3. Color framing
In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the phase
relationships between SYNC of the 1st field and sub-carrier are kept stable regardless of the power supply
being ON or OFF. However, as the PAL and PALM systems are comprised of PLL, the absolute values
concerning the phase according to variation of the ambient temperature drifts.
When the VRI is input as shown in figure below, OSYNC can be reset at the same phase with the SYNC signal.
Since the falling edge point in the diagram above (marked with ) is the boundary of reset, if the falling edge
of the VRI input traverses that point, it causes 1/2H deviation to the reset state.
Accordingly, if resetting is applied between two similar systems whose frequency are different, the V to which
resetting is applied generates jitter of 1/2H. (When the resetting is applied continuously.)
Phase relation between LALTRI pulse polarity and 2f
Resetting operation is basically required only in the external synchronizing mode (GEN LOCK mode). However,
even in the internal synchronizing mode, it sometimes requires H and V outputs whose phases are deviated
against a certain output. In that case, it suffices to use two CXD1217s and conduct the operation as follows:
By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 can be provided
against the respective OHD1 and OVD1.
After reset SYNC OUT
SYNC Signal
Counter State
CXD1217 internal clock (2f
(See Timing Chart Diagram)
VRI
OHD1 OVD1
1
CXD1217
2
V reset pulse
Input
3
Shift Reg.
H
4
)
Clock
5
Delay
6
Output
7
– 6 –
H
is the same as in the case of V resetting.
It suffices to set IC-1 and IC-2 into INT mode.
8
Reset State
a
VRI2
VRI2
Rising edge is to be behind from point
OHD2
9
Falling edge permitted span
9
CXD1217
10
10
OVD2
11
11
Clock
12
12
13
13
14
14
a
15
CXD1217Q

Related parts for cxd1217q