cxd1944r Sony Electronics, cxd1944r Datasheet - Page 16

• Manufacturer Part Number: cxd1944r
• Description: Ieee1394 3-port 200mbps Cable Transceiver/arbiter
• Manufacturer: Sony Electronics

LREQ Timing
FairReq and PrioReq:
sends the request at least one clock after the interface
becomes idle. The LINK interprets the receive state on
the CTL pins as a lost request. If the LINK sees the
receive state anytime during or after it sends the request
transfer, it assumes the request is lost and reissues the
request on the next idle. The PHY will ignore a fair or pri-
ority request if it asserts the receive state anytime during
the request transfer. Note that the minimum length of a
packet is two clock cycles in the case of 400Mbps
acknowledge packet. The minimum request packet is 8
clock cycles. It is important that the LINK and PHY agree
to interpret a lost request the same way.
(PriReq) to send the cycle start message. To request the
bus to send isochronous data, the LINK can issue the
request at any time after receiving the cycle start. The
PHY will clear an isochronous request only when the bus
has been won.
ImmReq:
ImmReq request during the reception of the packet
addressed to it. This is required because the delay from
end of packet to acknowledge request adds directly to
the minimum delay every PHY must wait after every
packet to allow an acknowledge to occur. After the pack-
et ends, the PHY immediately takes control of the bus
and grants the bus to the LINK. If the header CRC of the
packet turns out to be bad, the LINK releases the bus
immediately. The LINK cannot use this grant to send
another type of packet. To ensure this, the LINK must
wait 160ns after the end of the received packet to allow
the PHY to grant it the bus for the acknowledge, then
release the bus and proceed with another request.
ferent nodes can perceive (one correctly, one mistaken-
ly) that an incoming packet is intended for them and both
issue an acknowledge request before checking the CRC.
Both nodes’ PHYs would grab control of the bus immedi-
ately after the packet is complete. This condition will
To request the bus for fair or priority access, the LINK
The cycle master node uses a priority request
To send an acknowledge, the LINK must issue an
Though highly unlikely, it is conceivable that two dif-
LR0
LR1
LR2
–16–
LR3
cause a temporary, localized collision of the data-on line
states somewhere between two PHYs intending to
acknowledge. All other PHYs on the bus would see the
data-on state. This collision would appear as a “zz” line
state, and would not be interpreted as a bus reset. The
mistaken node would drops its request as soon as it has
checked the CRC and spurious “zz” line states would go
away. The only side effect of such a collision would be
the loss of the intended acknowledge packet, which
would be handled by the higher-layer protocol.
IsoReq:
mended to issue an IsoReq request during the reception
or transmission (if root) of a cycle start packet or another
isochronous packet. This is required to keep an isochro-
nous gap short. Any IsoReq will be cleared when a pack-
et is transmitted or a certain time (80ns) is passed in idle
after the bus seized. (This timeout is not a part of the
IEEE1394-1995 standard.) When the LINK issues an
IsoReq before CRC check of a cycle start packet and the
CRC is found wrong after the IsoReq, the LINK may
release the bus without sending a packet when the bus is
granted.
Read/Write Request:
field of the transfer and loads it into the addressed regis-
ter as soon as the transfer is complete. For read
requests, the PHY returns the contents of the addressed
register at the next opportunity through a status transfer.
The LINK is allowed to perform a read or write operation
at any time. If the status transfer is interrupted by an
incoming packet, the PHY continues to attempt the trans-
fer of the requested register until it is successful.
(immediate, iso, fair, or priority) it cannot issue another
request until the PHY indicates “lost” (incoming packet)
or “won” (transmit). The PHY ignores new requests while
a previous request is pending.
To send an isochronous packet, the LINK is recom-
For write requests, the PHY takes the value in the data
Once the LINK issues a request for access to the bus
LR (n – 2)
LR (n – 1)
CXD1944R