cxd1159aq Sony Electronics, cxd1159aq Datasheet
cxd1159aq
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cxd1159aq Summary of contents
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... Sync Signal Generator for Camera Description The CXD1159AQ is a sync signal generator for consumer video cameras. Features • Adapts to NTSC or PAL through mode switching • Low power consumption • Phase comparator and built-in inverter for active filter (Power supply according to inverter for filter) • ...
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... SYNC BLKO 32 1/227 COMPARATOR 1/65 1/525 or 625 H-DECODER V-DECODER V-CONTROL OUTPUT CONTROL – 2 – CXD1159AQ 24 SC PHASE 17 COMP 16 PSEL 20 AOUT 19 AIN 13 SCOF 14 MODE 27 TEST 5 EXT VINT PSEL ...
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... Sub carrier output 25 WNDE I WND output enable input (at L: Enable) 26 WND O Window output 27 TEST I Test input (Normally "L" — +5V DD1 29 HDO O Horizontal drive pulse 30 VDO O Vertical drive pulse 31 SYNC O Composite sync pulse 32 BLKO O Composite blanking pulse Description – 3 – CXD1159AQ ...
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... –10 LZ Min. Typ. Max 2.4V 45 2.4V t PDH Typ. Max. Unit 9 pF Test Circuit 11 pF 600 V 1kHz – 4 – CXD1159AQ = 0V, Topr = –20 to +75°C) SS Typ. Max. Unit 4 0.1 mA – µA 10 µA ...
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... In INT mode the circuit is initialized with the fall of VINT. At that time and LALT resets are not accepted. In EXT mode, VINT is not accepted, whereas H, V and LALT resets are accepted. Master 4fsc COMP (908f ) H Fast Delay H Slow Fast L Fast Delay L Slow Fast H INT: Internal mode SC (EXT = L) 910f /4 H EXT: External mode 4fsc/4 (EXT = H) 4fsc/4 – 5 – CXD1159AQ ...
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... VD is reset 3.5H in advance of VR input. The minimum reset pulse width is 32µs. • LALT reset (LR) LALT is reset in the same phase as LR reset. The minimum reset pulse width is 32µs. LR LALT PAL VINT VD HD FLD Initialize point more than 0.98µs 2.94 to 3.43µs – 6 – CXD1159AQ ...
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... Timing Chart H (NTSC) 6.36 HDO 10.76 BLKO 4.89 HSYNC (SYNC) 1.47 2.45 EO (SYNC) 26.89 VSYNC (SYNC) 2.45 BFO 6.85 VD FLD ODD 28.36 WND Timing Chart H (PAL) 6.41 HDO 10.70 BLKO 4.93 HSYNC (SYNC) 1.48 2.47 EO (SYNC) 27.07 VSYNC (SYNC) 2.47 BFO 6.91 VD FLD ODD LALT 28.55 WND 1/2H 1.47 4.89 EVEN 17.6 1/2H 1.48 4.93 EVEN 17.69 – 7 – CXD1159AQ 1H (Unit: µs) 1H (Unit: µs) ...
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... FIELD II, IV HDO VDO SYNC BLKO BFO (IV – I) BFO (II – III) LALT (IV – I) LALT (II – III) FLD WND FIELD O 9H 20H 80H FIELD E 9H 20H 80.5H FIELD II, IV 7.5H 25H 97H FIELD I, III 7.5H 25H 96.5H – 8 – CXD1159AQ O: ODD E: EVEN 121H 121H 144H 144H ...
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... Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. H – 9 – CXD1159AQ 1M 1000p 100k 10k 0.01µ 100 ...
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... LEAD TREATMENT LEAD TREATMENT THICKNESS 32PIN QFP (PLASTIC 0.30 – 0.10 ( 0.30) DETAIL A : SOLDER PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SPEC. ALLOY 42 Sn-Pb 10% 5-18µm – 10 – CXD1159AQ 0.1 + 0.35 1.5 – 0. 0.2 0.1 – 0.1 0˚ to 10˚ EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 0.2g Sony Corporation ...