AD674 AD [Analog Devices], AD674 Datasheet - Page 3

• Manufacturer Part Number: AD674
• Description: Complete 12-Bit A/D Converters
• Manufacturer: AD [Analog Devices]

DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
V
V
I
I
C
LOGIC OUTPUTS
V
V
I
C
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
Parameter
Conversion Time
STS Delay from CE
CE Pulsewidth
CS to CE Setup
CS Low During CE High
R/C to CE Setup
R/C LOW During CE High t
A
A
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
Access Time
Data Valid After CE Low
Output Float Delay
CS to CE Setup
R/C to CE Setup
A
CS Valid After CE Low
R/C High After CE Low
A
NOTES
1
for an output to cross 0.4 V or 2.4 V.
2
3
4
5
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at T
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
t
0°C to T
At –40°C.
At –55°C.
t
IH
IL
OZ
DD
HL
0
0
0
0
IH
IL
OH
OL
IN
OZ
to CE Setup
Valid During CE High
to CE Setup
Valid After CE Low
8-Bit Cycle (AD674B)
12-Bit Cycle (AD674B) t
8-Bit Cycle (AD774B)
12-Bit Cycle (AD774B) t
C
is defined as the time required for the data lines to change 0.5 V when loaded with
is measured with the load circuit of Figure 3a and is defined as the time required
L
= 100 pF
MAX
.
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
Symbol
t
t
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
t
MIN
HRC
C
C
C
C
DSC
HEC
SSC
HSC
SRC
SAC
HAC
DD
HD
HL
SSR
SRR
SAR
HSR
HRR
HAR
5
1
, 25°C, and T
J, K, A, B Grades
Min Typ Max Min Typ Max Unit
6
9
4
6
50
50
50
50
50
0
50
J, K, A, B Grades
Min Typ
25
20
50
0
50
0
0
50
2
3
MAX
8
12
5
7.3
75
(For all grades T
V
. Results from those tests are used
EE
= –15 V
10
15
6
8
200
150
150
Max Min Typ Max Unit
(For all grades T
V
LOGIC
6
9
4
6
50
50
50
50
50
0
50
25
15
50
0
50
0
0
50
= +5 V
2
4
T Grade
T Grade
Test Conditions
V
V
I
I
V
10% or –12 V
8
12
5
7.3 8
75
OH
OL
MIN
IN
IN
IN
= 1.6 mA
to T
= 0 V
= 0.5 mA
= V
= 0 to V
10
15
6
225
150
150
MIN
MAX
10%, V
LOGIC
to T
with V
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LOGIC
MAX
EE
CC
= –15 V
5%, unless otherwise noted.)
with V
DB11 – DB0
= +15 V
DB11 – DB0
CC
STS
R/C
= +15 V
CE
CS
A
DB
DB
STS
R/C
CE
CS
0
A
10% or –12 V
N
N
Min
2.0
–0.5
–10
–10
2.4
–10
0
HIGH-Z TO LOGIC 1
LOGIC 1 TO HIGH-Z
IMPEDANCE
10% or +12 V
t
SRR
HIGH
t
3k
3k
SAC
t
10% or +12 V
SSR
t
t
SAR
SSC
t
SRC
100pF
100pF
t
t
5%, unless otherwise noted.)
t
HSC
t
HRC
DD
DSC
t
t
HAC
5%, V
HEC
Max
V
+0.8
+10
+10
10
0.4
+10
10
t
HSR
LOGIC
DB
DB
VALID
IMPEDANCE
DATA
N
N
LOGIC
HIGH-Z TO LOGIC 0
LOGIC 0 TO HIGH-Z
5%,
AD674B/AD774B
HIGH
t
+ 0.5
t
HD
HAR
= +5 V
t
C
5V
5V
t
t
HL
HRR
3k
3k
100pF
100pF
Unit
V
V
µA
µA
pF
V
V
µA
pF
10%,
IMPEDANCE
HIGH