FS450 ETC2 [List of Unclassifed Manufacturers], FS450 Datasheet - Page 52

• Manufacturer Part Number: FS450
• Description: i-Net TV Interface Video Processor
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

FS450, FS451
7. Design and Layout Considerations
Careful circuit design and layout are key factors that insure a successful implementation of the FS450 in a
product. The following guidelines will help insure that your design yields the best possible results.
7.1 Pixel Phase Lock Loop
7.2 Video Output Filters
7.3 Analog Power Supply Bypassing, Filtering, and Isolation
7.4 Power and Ground
JUNE, 2000, VERSION 1.2
The analog supply for the Pixel PLL should always be clean and noise free to insure minimum jitter in
the PLL. Do not power other circuitry from the PLL supply.
The supply line V
capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100 F. Always have a 1000pF to 0.1 F
capacitor to remove high frequency noise.
Use a solid ground plane under the FS450.
To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75W
termination resistors and the first capacitor of the output filter close to the video output pins of the
FS450.
When possible, it is recommended that the analog supply voltages be fed from a linear voltage regulator.
Switching power supply noise, and noise from the digital plane can induce visible artifacts into the
displayed video. Always provide sufficient filtering and high frequency bypassing to insure that power
supply noise is minimized for visual as well as EMI reasons.
It is recommended that each power supply section be isolated with a ferrite bead and a 4.7 F capacitor.
Where the power pins are so close together that the 0.1 F bypass capacitors are adjacent, consider
changing one of the adjacent capacitors to 100 to 1000pF to reduce higher frequency noise on the
power supply.
Within the FS450, separate power is routed to functional sections: phase locked loop, D/A converters,
digital processors and digital drivers. All ground pins should be connected to a common ground plane.
Power pins should be segregated into analog and digital sections.
Clean analog power should be applied to the V
be placed adjacent to each group of pins. The capacitor connected to C
connected to V
Digital power may be derived from system digital +3.3 volts. If necessary insert a ferrite bead in series
with the supply trace. A 47 F capacitor should be placed across the common +3.3 VDC for V
V
one 0.1 F capacitor should be located adjacent to V
transient currents.
DDDA
to act as a reservoir for heavy currents drawn by D/A converters and internal memories. At least
DDDA
DDPA
to minimize noise at the D/A converter outputs. Chip capacitors are recommended.
should be decoupled with a series resistor of 150W and a 4.7 F tantalum
DDPA
52
, V
DD
DDOSC
COPYRIGHT
pins along each side of the FS450 to supply
, and V
DDDA
1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY PRODUCT DESCRIPTION
pins. A 0.1 F capacitor should
BYPASS
is critical, and it must be
PRELIMINARY INFORM ATION
DD
and