74ACQ240PC Fairchild Semiconductor, 74ACQ240PC Datasheet

74ACQ240PC

Manufacturer Part Number

74ACQ240PC

Description

IC INVERTER DUAL 4-INPUT 20DIP

Manufacturer

Fairchild Semiconductor

Series

74ACQr

Datasheet

1.74ACQ240PC.pdf (10 pages)

Specifications of 74ACQ240PC

Logic Type

Inverter

Number Of Inputs

Number Of Circuits

Current - Output High, Low

24mA, 24mA

Voltage - Supply

2 V ~ 6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Through Hole

Package / Case

20-DIP (0.300", 7.62mm)

Logic Family

ACQ

Number Of Channels Per Chip

Polarity

Inverting

Supply Voltage (max)

6 V

Supply Voltage (min)

2 V

Maximum Operating Temperature

+ 85 C

Mounting Style

Through Hole

High Level Output Current

- 24 mA

Low Level Output Current

24 mA

Minimum Operating Temperature

- 40 C

Number Of Lines (input / Output)

8 / 3

Output Type

3-State

Propagation Delay Time

10 ns at 3.3 V, 6.5 ns at 5 V

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

74ACQ240

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74ACQ240SC

74ACQ240SJ

74ACQ240PC

74ACTQ240SC

74ACTQ240SJ

74ACTQ240QSC

74ACTQ240PC

74ACQ240 • 74ACTQ240

Quiet Series

with 3-STATE Outputs

General Description

The ACQ/ACTQ240 is an inverting octal buffer and line

driver designed to be employed as a memory address

driver, clock driver and bus oriented transmitter or receiver

which provides improved PC board density. The ACQ/

ACTQ utilizes Fairchild’s Quiet Series

guarantee quiet output switching and improve dynamic

threshold performance. FACT Quiet Series

GTO

to a split ground bus for superior performance.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

FACT , Quiet Series , FACT Quiet Series , and GTO

Order Number

output control and undershoot corrector in addition

Package Number

MQA20

M20B

M20D

M20B

M20D

N20A

Octal Buffer/Line Driver

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

technology to

are trademarks of Fairchild Semiconductor Corporation.

DS010234

features

Features

Pin Descriptions

Guaranteed simultaneous switching noise level and

dynamic threshold performance

Guaranteed pin-to-pin skew AC performance

Improved latch-up immunity

Inverting 3-STATE outputs drive bus lines or buffer

memory address registers

Outputs source/sink 24 mA

Faster prop delays than the standard ACT240

–I

–O

Pin Names

and I

Package Description

, OE

reduced by 50%

3-STATE Output Enable Inputs

Inputs

Outputs

July 1989

Revised October 2000

Description

www.fairchildsemi.com

Related parts for 74ACQ240PC

74ACQ240PC Summary of contents

Page 1

... M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACQ240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACQ240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide ...

Page 2

Logic Symbol Truth Tables HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.com IEEE/IEC Inputs Outputs I (Pins 12, 14, 16, 18 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

DC Electrical Characteristics for ACQ Symbol Parameter V Quiet Output OLP Maximum Dynamic Quiet Output OLV Minimum Dynamic Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW Level Dynamic Input Voltage ILD Note ...

Page 5

AC Electrical Characteristics for ACQ Symbol Parameter t Propagation Delay PHL t Data to Output PLH t Output Enable Time PZL t PZH t Output Disable Time PHZ t PLZ t Output to Output Skew OSHL t Data to Output ...

Page 6

FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide Package Number MQA20 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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