AD636 AD [Analog Devices], AD636 Datasheet - Page 5

• Manufacturer Part Number: AD636
• Description: Low Level, True RMS-to-DC Converter
• Manufacturer: AD [Analog Devices]

The primary disadvantage in using a large C
is that the settling time for a step change in input level is in-
creased proportionately. Figure 5 shows the relationship be-
tween C
microfarad of C
creasing signals as for increasing signals (the values in Figure 5
are for decreasing signals). Settling time also increases for low
signal levels, as shown in Figure 6.
A better method for reducing output ripple is the use of a
“post-filter.” Figure 7 shows a suggested circuit. If a single pole
filter is used (C3 removed, R
mately 5 times the value of C
in Figure 8, and settling time is increased. For example, with
C
duced from 10% of reading to approximately 0.3% of reading.
The settling time, however, is increased by approximately a
factor of 3. The values of C
to permit faster settling times while still providing substantial
ripple reduction.
The two-pole post-filter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The values
of C
settling times for a constant amount of ripple. Caution should
be exercised in choosing the value of C
dependent upon this value and is independent of the post filter.
For a more detailed explanation of these topics refer to the
RMS-to-DC Conversion Application Guide, 2nd Edition, available
from Analog Devices.
REV. B
AV
Figure 5. Error/Settling Time Graph for Use with the
Standard rms Connection
AV
= 1 F and C2 = 4.7 F, the ripple for a 60 Hz input is re-
0.01
100
1.0
0.1
10
, C2, and C3 can then be reduced to allow extremely fast
1
AV
10.0
7.5
5.0
2.5
1.0
VALUES FOR C
1% SETTLING TIME FOR
STATED % OF READING
AVERAGING ERROR*
ACCURACY
COMPONENT TOLERANCE
*% dc ERROR + % RIPPLE (PEAK)
1mV
0
and 1% settling time is 115 milliseconds for each
Figure 6. Settling Time vs. Input Level
AV
10
. The settling time is twice as great for de-
20% DUE TO
AV
INPUT FREQUENCY – Hz
AND
10mV
100
AV
rms INPUT LEVEL
X
AV
and C2 can therefore be reduced
shorted), and C2 is approxi-
, the ripple is reduced as shown
1k
AV
100mV
, since the dc error is
AV
10k
to remove ripple
100k
100
10
1.0
0.1
0.01
1V
–5–
RMS MEASUREMENTS
AD636 PRINCIPLE OF OPERATION
The AD636 embodies an implicit solution of the rms equation
that overcomes the dynamic range as well as other limitations
inherent in a straightforward computation of rms. The actual
computation performed by the AD636 follows the equation:
Figure 9 is a simplified schematic of the AD636; it is subdivided
into four major sections: absolute value circuit (active rectifier),
squarer/divider, current mirror, and buffer amplifier. The input
voltage, V
current I
the squarer/divider, which has the transfer function:
The output current, I
mirror through a low-pass filter formed by R1 and the externally
connected capacitor, C
greater than the longest period of the input signal, then I
effectively averaged. The current mirror returns a current I
which equals Avg. [I
the implicit rms computation. Thus:
–V
Figure 8. Performance Features of Various Filter Types
V
IN
S
C2
+
C
AV
–
0.1
10
+
–
1
1
, by the active rectifier A
10
IN
1
2
3
4
5
6
7
, which can be ac or dc, is converted to a unipolar
AD636
– BUF
+
Figure 7. 2 Pole ‘’Post’’ Filter
10k
ABSOLUTE
p-p RIPPLE
(ONE POLE)
C
C2 = 4.7 F
SQUARER
CURRENT
AV
DIVIDER
MIRROR
VALUE
10k
4
Rx
V rms
I
= 1 F
], back to the squarer/divider to complete
4
4
, of the squarer/divider drives the current
AV
DC ERROR
C
(ALL FILTERS)
10k
100
AV
p-p RIPPLE
(TWO POLE)
C
. If the R1, C
Avg.
AV
FREQUENCY – Hz
= 1 F
= 1 F, C2 = C3 = 4.7 F
I
4
Avg.
14
13
12
10
11
9
8
C3
I
I
1
4
I
2
I
1
1
3
2
–
+
, A
V rms
(FOR SINGLE POLE, SHORT Rx,
REMOVE C3)
V
p-p RIPPLE
C
+V
2
V
I
AV
IN
AV
. I
1
rms
S
1k
rms
= 1 F (FIG 1)
2
1
time constant is much
OUT
drives one input of
AD636
10k
4
is
3
,