SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet - Page 15

• Manufacturer Part Number: SST49LF004B-33-4C-EI
• Description: 4 Mbit LPC Firmware Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

4 Mbit LPC Firmware Flash
SST49LF004B
LPC Memory Write Cycle
TABLE 7: LPC M
©2003 Silicon Storage Technology, Inc.
LFRAME#
LAD[3:0]
FIGURE 7: LPC M
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
LCLK
3-10
11
12
13
14
15
16
17
1
2
CYCTYPE +
START
ADDR
SYNC
Name
Field
DATA
DATA
TAR0
TAR1
TAR0
TAR1
EMORY
DIR
EMORY
1 Clock 1 Clock
Start
0000b
W
CYCTYPE
011Xb
RITE
DIR
W
Field Contents
+
1111 (float)
1111 (float)
RITE
LAD[3:0]
C
A[31:28] A[27:24]
YYYY
ZZZZ
011X
0000
1111
0000
1111
ZZZZ
YCLE
C
YCLE
F
1
IELD
A[23:20] A[19:16]
W
Load Address in 8 Clocks
AVEFORM
D
OUT then Float
Float then OUT
EFINITIONS
Float then IN
Address
Direction
LAD[3:0]
OUT
IN
IN
IN
IN
IN
IN
A[15:12]
15
A[11:8]
Comments
LFRAME# must be active (low) for the device to
respond. Only the last field latched before LFRAME#
transitions high will be recognized. The START field
contents (0000b) indicate an LPC Memory cycle.
Indicates the type of LPC Memory cycle. Bits 3:2
must be “01b” for memory cycle. Bit 1 indicates the
type of transfer “1” for Write. Bit 0 is reserved.
Address Phase for Memory Cycle. LPC protocol sup-
ports a 32-bit address phase. YYYY is one nibble of
the entire address. Addresses are transferred most
significant nibble first.
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the host drives the bus to all '1's and
then floats the bus. This is the first part of the bus “turn-
around cycle.”
The SST49LF004B takes control of the bus during this
cycle.
The SST49LF004B outputs the values 0000, indicating
that it has received data or a flash command.
In this clock cycle, the SST49LF004B drives the bus to
all '1's and then floats the bus. This is the first part of
the bus “turnaround cycle.”
Host resumes control of the bus during this cycle.
A[7:4]
A[3:0]
Load Data in 2 Clocks
Data
D[3:0]
Data
D[7:4]
TAR0
1111b Tri-State
2 Clocks
TAR1
1 Clock
S71232-02-000
0000b
Sync
Data Sheet
1232 F06.1
TAR
T7.0 1232
12/03