ISL28210 INTERSIL [Intersil Corporation], ISL28210 Datasheet - Page 14

• Manufacturer Part Number: ISL28210
• Description: Precision Low Noise JFET Operational Amplifiers
• Manufacturer: INTERSIL [Intersil Corporation]

Typical Performance Curves
FIGURE 39. SETTLING TIME (t
Applications Information
Functional Description
The ISL28110 and ISL28210 are single and dual 12.5
MHz precision JFET input op amps. These devices are
fabricated in the PR40 Advanced Silicon-on-Insulator
(SOI) bipolar-JFET process to ensure latch-free
operation. The precision JFET input stage provides low
input offset voltage (300µV max @ +25°C), low input
voltage noise (6nV/√Hz), and input current noise that is
very low with virtually no 1/f component. A high current
complementary NPN/PNP emitter-follower output stage
provides high slew rate and maintains excellent THD+N
performance into heavy loads (0.0003% @ 10V
1kHz into 600Ω).
Operating Voltage Range
The devices are designed to operate over the 9V (±4.5V)
to 40V (±20V) range and are fully characterized at 10V
(±5V) and 30V (±15V). The JFET input stage maintains
high impedance over a maximum input differential
FIGURE 37. LARGE SIGNAL 10V STEP RESPONSE A
100
0.1
10
1
-2
-4
-6
6
4
2
0
1
0
V
V
R
V
A
R
C
S
OUT
L
S
V
L
L
= ±15V
= 2kΩ
= 2k
= 4pF
= ±15V
= -1
1
= 10V
2
P-P
CLOSED LOOP GAIN (V/V)
3
0.01%
14
4
TIME (µs)
10
5
S
) vs CLOSED LOOP GAIN
0.1%
6
7
ISL28110, ISL28210
8
9
P-P
V
@
10
100
= -1
V
specified. (Continued)
S
= ±15V, V
FIGURE 38. LARGE SIGNAL 10V STEP RESPONSE
voltage range of ±33V. Internal ESD protection diodes
clamp the non-inverting and inverting inputs to one diode
drop above and below the V+ and V- the power supply
rails (“Pin Descriptions” on page 2, CIRCUIT 1).
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V
reverse breakdown voltage which enables the device to
function reliably in large signal pulse applications without
the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. No
special input signal restrictions are needed for power
supply operation up to ±15V, and input signal distortion
caused by nonlinear clamps under high slew rate
conditions are avoided. For power supply operation
greater than ±16V (>32V), the internal ESD clamp
diodes alone cannot clamp the maximum input
differential signal to the power supply rails without the
risk of exceeding the 33V breakdown of the JFET gate.
Under these conditions, differential input voltage limiting
is necessary to prevent damage to the JFET input stage.
CM
1000
0.01
100
0.1
10
= 0V, R
-2
-4
-6
1
6
4
2
0
10
0
V
A
R
C
V
S
V
S
L
L
= +10
= 2k
= 4pF
FIGURE 40. Z
= ±15V
= ±15V
A
1
L
100
V
= Open, T = +25°C, unless otherwise
= +10
2
G = 100
1k
3
FREQUENCY (Hz)
OUT
4
10k
G = 10
TIME (µs)
vs FREQUENCY
5
100k
6
1M
7
G = 1
8
December 8, 2010
10M
9
100M
FN6639.1
10