ls7266r1 LSI Computer Systems, Inc., ls7266r1 Datasheet - Page 6

• Manufacturer Part Number: ls7266r1
• Description: 24-bit Dual-axis Quadrature Counter
• Manufacturer: LSI Computer Systems, Inc.

7266R1-101904-6
Transient Characteristics. (T
For V
Read Cycle
RD Pulse Width
CS Set-up Time
CS Hold Time
C/D Set-up Time
C/D Hold Time
X/Y Set-up Time
X/Y Hold Time
Data Bus Access Time
Data Bus Release Time
Back to Back Read delay
Write Cycle
WR Pulse Width
CS Set-up Time
CS Hold Time
C/D Set-up Time
C/D Hold Time
X/Y Set-up Time
X/Y Hold Time
Data Bus Set-up Time
Data Bus Hold Time
Back to Back Write Delay
Load CNTR, Reset CNTR and
Load OL Pulse Width
For V
Quadrature Mode
FCK High Pulse Width
FCK Low Pulse Width
FCK Frequency
Mod-n Filter Clock(FCKn)Period
FCKn frequency
Quadrature Separation
Quadrature Clock Pulse Width
Quadrature Clock frequency
Quadrature Clock to Count Delay
x1/x2/x4 Count Clock Pulse Width
Index Input Pulse Width
Index Skew from A
Carry/Borrow/Compare Output Width
Non-Quadrature Mode
Clock A - High Pulse Width
Clock A - Low Pulse Width
Direction Input B Set-up Time
Direction Input B Hold Time
Gate Input (ABG) Set-up Time
Gate Input (ABG) Hold Time
Clock Frequency
Clock to Carry or Borrow Out Delay
Carry or Borrow Out Pulse Width
Clock to Compare Out Delay
Parameter
DD
DD
= 3V to 5.5V:
= 3.3V
(See Fig. 1)
(See Fig. 2)
±
10%:
(See Fig. 3-5)
(See Fig. 6-7)
A
Symbol
= -25˚C to +80˚C)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
t
t
f
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
W10
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
W1
W2
W3
W4
W5
W6
W7
W8
W9
11
1
2
FCK
3
FCKn
4
5
QA
Q1
Q2
idx
Ai
Q3
6
7
8S
8H
GS
GH
A
9
10
12
,
f
QB
Min. Value
80
80
80
10
80
10
80
-
90
45
45
45
10
45
10
45
10
90
35
28
28
-
56
-
115
230
-
5t
56
170
-
56
30
30
40
20
40
20
-
-
28
80
0
0
3
Max.Value
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17
-
17
-
-
2.2
6t
-
-
56
-
-
-
-
-
-
-
16
50
-
-
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
ns
ns
MHz
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
Remarks
-
-
-
-
-
-
-
Access starts when both RD
and CS are low.
Release starts when either RD
or CS is terminated.
-
-
-
-
-
-
-
-
-
-
-
-
-
t
where n = PSC = 0 to FF
t
t
f
-
t
t
t
t
-
-
-
-
-
-
-
f
-
t
-
-
3
-
4
5
QA
Q2
idx
Ai
Q3
A
10
= (n+1) (t
= (1/ (t
= t
= t
= t
= f
2t
4t
t
3
3t
3
3
3
7
QB
3
3
= 1/8t
6
+ t
1
+t
7
2
3
) )
),
H