cxa1812q Sony Electronics, cxa1812q Datasheet - Page 16

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cxa1812q

Manufacturer Part Number
cxa1812q
Description
S-terminal Compatible Video I/o
Manufacturer
Sony Electronics
Datasheet
Description of Operation
(Refer to the Pin Description for details on the standard I/O signal levels and the control logic.)
The Y signals input to Pins 23 (YIN1) and 25 (YIN2) are clamped by the respective sync tips, and one of the
signals is selected by the control signal input to Pin 24 (INSEL). Titles are inserted by the control signals input
to Pins 16 (VOB) and 18 (VOW), and after passing through the buffer the signal is output from Pin 17
(YOUT1). Regarding the title insertion levels, the white level is approximately 75IRE and the black level is
approximately 10IRE. Title insertion is described in detail later.
Just as with the Y signals, one of the C signals input to Pins 27 (CIN1) and 29 (CIN2) is selected by the control
signal at Pin 24. The signal is muted to the chroma center level by the control signals at Pins 16 and 18, and
after being branched to EE output, the signal passes through the buffer and is output from Pin 15 (COUT1).
From the video
signal processing
block
• Video Input System
• Video Output System
CIN
YIN
YIN1
YIN2
CIN1
CIN2
13
7
23
25
27
29
C output system
Y output system
From C input system(EE)
Y input system
C input system
CLAMP
CLAMP
CLAMP
L
H
SEL2
6
L
H
L
H
INSEL
To VFY output system
24
CMUTE
To VFC output system
MUTE 3
—16—
4
VOB
16
To C output system (EE)
MUTE 1
and VFC output system
DDS 1
VOW
18
DRIV
DRIV
BUFF
BUFF
BUFF
YINVIN
P.SAVE
12
31
32
5
3
220µ
17
15
YOUT
COUT
COUT2
2.2µ
0.01µ
To composite
video signal
generation circuit
To video signal
processing block
YOUT1
COUT1
330
1k
75
75
External
video
output
CXA1812Q

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