SDA5252 SIEMENS [Siemens Semiconductor Group], SDA5252 Datasheet - Page 20

• Manufacturer Part Number: SDA5252
• Description: TVTEXT 8-Bit Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
6.2
The display features of SDA525x are similar to the Siemens SDA5248 TTX controller.
The display generator reads character addresses and control characters from the
display memory, selects the pixel information from the character ROM and translates it
into RGB values corresponding to the World Standard Teletext Norm. The national
option character bits for 11 languages inclusive X/26 characters are also supported.
6.2.1
A page consists of 25 rows of 40 characters each. One character covers a matrix of
12 horizontal and 10 vertical pixels. The pixel frequency should be 12 MHz
corresponding to 1 s for one character and 40 s for one row. A total of 250 TV lines
are used for TTX display. The display can be shifted horizontally from 0 s to 21.33 s
with respect to HS and vertically from line 1 (314) to line 64 (377) with respect to VS. The
display position is determined by the registers DHD and DVD.
Note: To avoid interferences between the subharmonics of the 18 MHz controller clock
6.2.2
A cursor is available which changes foreground to background colour for one character.
Cursor flash can be realized via software enabling/disabling the cursor. The cursor
position is defined by cursor position registers DCRP and DCCP.
6.2.3
A character background flash (character is changed to background colour) is realized by
hardware. The flash frequency is 1 Hz with a duty cycle of 32:18.
6.2.4
The SDA 525x delivers the new full screen background colour feature. Special function
register SFR DTIM(7-5) includes three bits which define the default background colour
for the inner and outer screen area.
6.2.5
The clear page logic generates a signal which is interpreted by the character generator
to identify non displayable rows. In row 25 specific information is stored by the
microcontroller indicating which of the rows 0 - 24 should be interpreted as erased during
character generation. At the beginning of each row the special control characters are
read from the display memory (see Table 3).
and the 12 MHz pixel clock, a pixel clock of about 11,5 MHz is recommended.
Display Generator
Display Format and Timing
Display Cursor
Flash
Full Screen Background Colour
Clear Page Logic
20
SDA 525x
1998-04-08