SST29EE020-150-4C-U2 SST [Silicon Storage Technology, Inc], SST29EE020-150-4C-U2 Datasheet - Page 5

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SST29EE020-150-4C-U2

Manufacturer Part Number
SST29EE020-150-4C-U2
Description
2 Mbit (256K x8) Page-Mode EEPROM
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet
2 Mbit Page-Mode EEPROM
SST29EE020 / SST29LE020 / SST29VE020
Data Sheet
TABLE 2: P
©2001 Silicon Storage Technology, Inc.
Symbol
A
A
DQ
CE#
OE#
WE#
V
V
NC
17
6
DD
SS
FIGURE 2: P
FIGURE 3: P
-A
-A
7
-DQ
0
7
0
Pin Name
Row Address Inputs
Column Address Inputs
Data Input/output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
IN
D
IN
IN
ESCRIPTION
A
A
SSIGNMENTS FOR
SSIGNMENTS FOR
WE#
V DD
A11
A13
A14
A17
A16
A15
A12
NC
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Functions
To provide memory addresses. Row addresses define a page for a Write cycle.
Column Addresses are toggled to load page data
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide:
Unconnected pins.
32-
32-
LEAD
PIN
DQ0
DQ1
DQ2
V SS
A16
A15
A12
NC
A7
A6
A5
A4
A3
A2
A1
A0
PDIP
Standard Pinout
TSOP
5.0V supply (±10%) for SST29EE020
3.0V supply (3.0-3.6V) for SST29LE020
2.7V supply (2.7-3.6V) for SST29VE020
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Top View
Die Up
Top View
32-pin
PDIP
5
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
307 ILL F19.0
V DD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
307 ILL F01.2
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
S71062-06-000 6/01
T2.2 307
307

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