IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet - Page 19

• Manufacturer Part Number: IDT72261
• Description: CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72261/72271 SyncFIFO
16,384 x 9, 32,768 x 9
Q
D
NOTES:
1. t
2.
WCLK
RCLK
WEN
0
REN
0
OE
FF
- D
- Q
LD
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t
WCLK cycle.
SKEW1
8
8
= HIGH
LOW
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
DATA IN OUTPUT REGISTER
t
NO WRITE
ENS
t
SKEW1
t
ENH
t
(1)
A
1
Figure 9. Full Flag Timing (IDT Standard Mode)
2
t
WFF
t
DS
t
Wd
WFF
DATA READ
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SKEW1
t
ENS
NO WRITE
, then the
FF
t
will go high (after one WCLK cycle pus t
SKEW1
t
FF
ENH
t
deassertion may be delayed an extra
(1)
A
1
NEXT DATA READ
DATA
WRITE
2
t
WFF
3036 drw 12
t
DS
WFF
19
).