mws5101 Intersil Corporation, mws5101 Datasheet
mws5101
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mws5101 Summary of contents
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... Copyright Description The MWS5101 and MWS5101A are 256 word by 4-bit static random access memories designed for use in memory systems where high speed, very low operating current, and simplicity in use are desirable. They have separate data inputs and outputs and utilize a single power supply ...
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... FUNCTION † 20 CONTROL R/W B † 19 CONTROL CSI † CS2 † † INPUT PROTECTION † † NETWORK MWS5101, MWS5101A OPERATIONAL MODES INPUTS CHIP SELECT 2 OUTPUT (CS ) DISABLE ( 32) STORAGE STORAGE ...
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... IN Output Capacitance C OUT NOTES Typical values are for T = +25 C and nominal Outputs open circuited; Cycle time = 1 s. MWS5101, MWS5101A Thermal Information Thermal Resistance (Typical) PDIP Package . . . . . . . . . . . . . . . . . . . +0.5V SBDIP Package . . . . . . . . . . . . . . . . . . DD 10mA Operating Temperature Range (T Package Type .-55 Package Type .-40 Maximum Storage Temperature Range (T Maximum Junction Temperature Ceramic Package ...
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... WC 110 - - 150 - - 150 - - 110 - - 110 - - 110 - - , 100pF and MWS5101A DD. 6-59 L3 TYPES (NOTE 2) (NOTE 3) MIN TYP MAX UNITS 350 - - ns - 200 350 ns - 200 350 ns - 200 350 150 400 - - ns 150 - - ns 50 ...
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... OUTPUT DISABLE xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx DI1-DI4 xxxxxxxxxxxxxxxxxxxx READ/WRITE xxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxxx NOTE required for common I/O operation only; for separate I/O operations, output disable is “don’t care”. ODS MWS5101, MWS5101A DOA1 t DOA2 t DOA3 t AA HIGH FIGURE 1. READ CYCLE TIMING WAVEFORMS t ...
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... Typical Values are for and nominal V A DATA RETENTION MODE V DD 0. CDR FIGURE 3. LOW V DATA RETENTION TIMING WAVEFORMS DD MWS5101, MWS5101A +70 C; See Figure 3 A TEST CONDITIONS SYMBOL (V) ( ...
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... DISABLE FIGURE 5. LOGIC DIAGRAM OF CONTROLS FOR MWS5101, MWS5101A All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...