NJU26126_10 NJRC [New Japan Radio], NJU26126_10 Datasheet - Page 16

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NJU26126_10

Manufacturer Part Number
NJU26126_10
Description
Digital Signal Processor
Manufacturer
NJRC [New Japan Radio]
Datasheet
NJU26126
Note: If input and output of an audio signal stop and an audio interface stops, WDC can’t output.
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Pin setting
WatchDog Clock
The NJU26126 operates default command setting after resetting the NJU26126. In addition, the NJU26126
restricts operation at power on by setting PROC pin (No.17) (Table 15). This pin is input pin. However, this pin
operates as bi-directional pin. Connect with V
Table 15
The NJU26126 outputs clock pulse through WDC (No.18) pin during normal operation.
The NJU26126 generates a clock pulse through the WDC terminal after resetting the NJU26126. The WDC
clock is useful to check the status of the NJU26126 operation. For example, a microcomputer monitors the
WDC clock and checks the status of the NJU26126. When the WDC clock pulse is lost or not normal clock cycle,
the NJU26126 does not operate correctly. Then reset the NJU26126 and set up the NJU26126 again.
Watchdog clock output cycle is about 170msec.
That is because it has controlled based on the signal of an audio interface.
Pin No. Symbol
17
PROC
Pin setting
Setting
“High”
“Low”
Function
The NJU26126 does not operate after reset. Sending start
command is required for starting operation.
The NJU26126 operates default setting after reset. The default
value of Master Volume is Mute.
DD
or V
SS
through 3.3k
resistance.
Ver.2010-08-19

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