ACS8515REV2.1T SEMTECH [Semtech Corporation], ACS8515REV2.1T Datasheet - Page 3

• Manufacturer Part Number: ACS8515REV2.1T
• Description: Line Card Protection Switch for SONET or SDH Network Elements
• Manufacturer: SEMTECH [Semtech Corporation]

List of Figures
List of Figures
List of T
List of T
List of Figures
List of Figures
List of Figures
Figure 1. Simple Block Diagram .............................................................................................................................................................. 1
Figure 2. ACS8515 Pin Diagram ............................................................................................................................................................. 4
Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) .................................................................................................................... 11
Figure 4. Minimum Input Jitter Tolerance (DS1/E1) ........................................................................................................................... 12
Figure 5. Wander and Jitter Transfer Measured Characteristics ........................................................................................................ 14
Figure 6. Maximum Time Interval Error of TOUT0 Output Port ........................................................................................................... 15
Figure 7. Time Deviation of TOUT0 Output Port ................................................................................................................................... 15
Figure 8. Phase Error Accumulation of TOUT0 Output Port in Holdover Mode ................................................................................. 15
Figure 9. Inactivity and Irregularity Monitoring .................................................................................................................................... 30
Figure 10. Automatic Mode Control State Diagram ............................................................................................................................ 34
Figure 11. Recommended Line Termination for PECL Input/Output Ports ....................................................................................... 38
Figure 12. Recommended Line Termination for LVDS Input/Output Ports ....................................................................................... 39
Figure 13. Input/Output Timing ............................................................................................................................................................. 43
Figure 14. Serial Interface Read Access Timing .................................................................................................................................. 44
Figure 15. Serial Interface Write Access Timing ................................................................................................................................. 45
Figure 16. LQFP Package ....................................................................................................................................................................... 46
Figure 17. Typical 64 Pin LQFP Footprint .............................................................................................................................................. 47
Figure 18. Simplified Application Schematic ....................................................................................................................................... 48
List of T
List of T
List of Tables
Table 1. Power Pins .................................................................................................................................................................................... 5
Table 2. No Connections ............................................................................................................................................................................ 5
Table 3. Other Pins ..................................................................................................................................................................................... 6
Table 4. Input Reference Source Selection and Group Allocation ....................................................................................................... 9
Table 5. Input Reference Source Jitter Tolerance ................................................................................................................................ 10
Table 6. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 11
Table 7. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 12
Table 8. Output Reference Source Selection Table ............................................................................................................................. 13
Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 13
Table 10. Register Map ........................................................................................................................................................................... 18
Table 11. Register Map Description ...................................................................................................................................................... 21
Table 12. Absolute Maximum Ratings ................................................................................................................................................... 35
Table 13. Operating Conditions .............................................................................................................................................................. 35
Table 14. DC Characteristics: TTL Input Pad ......................................................................................................................................... 35
Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up ..................................................................................................... 36
Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down ................................................................................................ 36
Table 17. DC Characteristics: TTL Output Pad ...................................................................................................................................... 36
Table 18. DC Characteristics: PECL Input/Output Pad ....................................................................................................................... 37
Table 19. DC Characteristics: LVDS Input/Output Pad ....................................................................................................................... 38
Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813) .............................................................................. 39
Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) .............................................................................. 40
Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3) .............................................................. 40
Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) ................................................................ 41
Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411) ................................................................... 41
Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) .............................................................................. 42
Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499) ........................................................... 42
Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE) .............................................................. 42
Table 28. Serial Interface Read Access Timing .................................................................................................................................... 45
Table 29. Serial Interface Write Access Timing ................................................................................................................................... 45
Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) ...................................................................................... 47
Table 31. Revision History ...................................................................................................................................................................... 49
Revision 2.01/December 2005 Semtech Corp.
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ACS8515 Rev2.1 LC/P
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