LX8384-15 MICROSEMI [Microsemi Corporation], LX8384-15 Datasheet - Page 2

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LX8384-15

Manufacturer Part Number
LX8384-15
Description
5A LOW DROPOUT POSITIVE REGULATORS
Manufacturer
MICROSEMI [Microsemi Corporation]
Datasheet
LX8384-xx/8384A-xx/8384B-xx
2
* This pin GND for fixed voltage versions.
Power Dissipation .................................................................................. Internally Limited
Input Voltage ................................................................................................................ 10V
Input to Output Voltage Differential ........................................................................... 10V
Operating Junction Temperature
Storage Temperature Range ...................................................................... -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) ............................................................. 300°C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with
P PACKAGE:
DD PACKAGE:
Junction Temperature Calculation: T
The
All of the above assume no ambient airflow.
*
THERMAL RESISTANCE-JUNCTION TO TAB,
THERMAL RESISTANCE-JUNCTION TO AMBIENT,
THERMAL RESISTANCE-JUNCTION TO TAB,
THERMAL RESISTANCE-JUNCTION TO AMBIENT,
plane or internal power plane.
mounting technique.
Hermetic (K - Package) ........................................................................................ 150°C
Plastic (DD - Package) .......................................................................................... 150°C
JA
can be improved with package soldered to 0.5IN
ADJ or
JA
GND*
numbers are guidelines for the thermal performance of the device/pc-board system.
respect to Ground. Currents are positive into, negative out of the specified terminal.
V
IN
A B S O LUT E MAXIMU M RATINGS
Circuit
Bias
T H E R M A L D ATA
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
JA
can vary from 20ºC/W to > 40ºC/W depending on
J
Limit Circuit
= T
5 A L
Thermal
A
+ (P
P
JT
JT
O W
D
R O D U C T I O N
x
JA
JA
JA
D
).
2
copper area over backside ground
R O P O U T
Bandgap
B L O C K D I A G R A M
Circuit
P
(Note 1)
O S I T I V E
D
A T A
Control
Circuit
60°C/W*
2.7°C/W
2.7°C/W
60°C/W
R
S
E G U L A T O R S
H E E T
Output
Circuit
SOA Protection
Limit Circuit
Current
Circuit
* Pin 1 is GND for fixed voltage versions.
* Pin 1 is GND for fixed voltage versions.
PACKAGE PIN OUTS
TAB IS V
TAB IS V
DD PACKAGE
P PACKAGE
OUT
(Top View)
(Top View)
3
2
1
OUT
3
2
1
V
ADJ / GND*
V
V
IN
OUT
Copyright © 1997
Rev. 1.9
OUT
V
ADJ / GND*
V
IN
OUT
12/97

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