IDT2309A-1PGG IDT [Integrated Device Technology], IDT2309A-1PGG Datasheet - Page 6
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IDT2309A-1PGG
Manufacturer Part Number
IDT2309A-1PGG
Description
3.3V ZERO DELAY CLOCK BUFFER
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.IDT2309A-1PGG.pdf
(8 pages)
ZERO DELAY AND SKEW CONTROL
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
Output
SWITCHING WAVEFORMS
IDT2309A
3.3V ZERO DELAY CLOCK BUFFER
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
t3
0.8V
1.4V
All Outputs Rise/Fall Time
2V
Duty Cycle Timing
t2
1.4V
2V
t1
0.8V
t4
1.4V
3.3V
0V
6
CLK OUT
CLK OUT
Device 2
Device 1
Output
Output
Output
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
REF
t7
t5
t6
1.4V
Input to Output Propagation Delay
V
V
DD
DD/
Output to Output Skew
Device to Device Skew
/2
2
V
1.4V
DD/
V
2
DD
/2