S1D13305D00A EPSON [Epson Company], S1D13305D00A Datasheet - Page 18
S1D13305D00A
Manufacturer Part Number
S1D13305D00A
Description
LCD Controller ICs
Manufacturer
EPSON [Epson Company]
Datasheet
1.S1D13305D00A.pdf
(94 pages)
- Current page: 18 of 94
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SPECIFICATIONS
6.3.3. Display memory read timing
12
T
EXT 0
VD0 to
a
Signal Symbol
VA0 to
VA15
VCE
VRD
VD7
= –20 to 75 C
VA0 to VA15
VD0 to VD7
EXT 0
VR/W
VCE
t
t
t
t
t
t
t
t
t
RCH
t
CYR
ASC
AHC
RCS
ACV
CEA
OH2
CE3
t
t
CE
W
C
Clock period
VCE HIGH-level
pulsewidth
VCE LOW-level
pulsewidth
Read cycle time
Address setup time to
falling edge of VCE
Address hold time from
falling edge of VCE
Read cycle setup time to
falling edge of VCE
Read cycle hold time
from rising edge of VCE
Address access time
VCE access time
Output data hold time
VCE to data off time
Parameter
t
t
C
W
t
RCS
t
ASC
t
ACV
t
CEA
2t
2t
V
t
t
t
C
C
C
DD
0.5t
C
C
Min.
100
3t
EPSON
t
CYR
—
—
– 50
– 70
– 45
0
0
– 30
– 30
C
= 4.5 to 5.5V V
C
t
t
3t
AHC
CE
2t
C
Max.
C
—
—
—
—
—
—
—
—
—
—
– 100
– 80
2t
t
2t
t
C
t
C
C
DD
0.5t
Min.
C
C
125
3t
– 100
—
—
– 50
– 60
0
0
– 30
– 40
C
= 2.7 to 4.5V
C
t
CE3
3t
2t
C
Max.
C
—
—
—
—
—
—
—
—
—
—
– 115
– 90
t
RCH
t
t
W
OH2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S1D13305 Series
Technical Manual
Condition
CL = 100
pF
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