CMPWR160SA CALMIRCO [California Micro Devices Corp], CMPWR160SA Datasheet - Page 3

• Manufacturer Part Number: CMPWR160SA
• Description: USB peripheral Power Management
• Manufacturer: CALMIRCO [California Micro Devices Corp]

©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
12/5/2000
Interface Signals
V
Regulator, capable of delivering 3.3V/500mA output
current even when the input is as low as 4.2V.
Internal loading on this pin is typically 35µA when the
regulator is enabled, which reduces to only 7µA when-
ever the regulator is shutdown (
event of V
immediately reduce to less than 0.1µA.
If the V
filter, a capacitor may not be necessary. Otherwise an
input filter capacitor in the range of 1µF to 10µF will
ensure adequate filtering.
SD
Active Low. This is a true CMOS input signal referenced
to V
regulator operates fully. When the pin is taken to GND,
the device enters shutdown mode and the regulator is
fully disabled. In this mode all critical
remains fully powered consuming less than 7µA (typical).
V
load. An output capacitor of 10µF is used to provide the
necessary phase compensation, thereby preventing
oscillation. The capacitor also helps to minimize the peak
output disturbance during line or load transients. When-
ever V
CC
OUT
Symbol
215 Topaz Street, Milpitas, California 95035 
V
GND
POR
CALIFORNIA MICRO DEVICES
is the regulator shutdown input logic signal which is
V
is the input power source for the Low Drop Out
CC
SD
OUT
is the regulator output voltage used to power the
CC
CC
supply. When the pin is tied High (V
CC
collapses below the output the device immedi-
pin is within a few inches of the main input
CC
collapsing below V
Positive supply input for regulator. When V
Shutdown control input signal (Active Low) to disable internal voltage regulator and current supply
to less than 7µA.
Power-On-Reset output signal is held Low until the output has been stable (>2.9V) for at least 30ms.
Regulator voltage ouput (3.3V) capable of delivering 500mA when device is enabled (SD is High).
Whenever the output exceeds 2.9V (TYP) the POR pulse is triggered.
Negative reference for all voltages
V
CC
5V
OUT
SD
+
–
, the loading at V
taken Low). In the
+
POR
C
1µF
IN
CC
circuitry
) the
Typical Application Circuit
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V
SD
CMPWR160
Pin Functions
CC
CC
CC
will
GND
falls below V
V
POR
Description
OUT
ately enters reverse protection mode to prevent any
current flow back into the regulator pass transistor.
Under these conditions V
the necessary quiescent current for the internal refer-
ence and
characteristics for the regulator.
POR
When V
(typically 2.9V), the pin is forced to logic low (GND). The
pin remains logic low for 30ms then it is forced logic high
(3.3V). If V
during this 30ms interval
falls below the voltage threshold and then recovers the
30ms time will reset.
If V
immediately forced to logic low.
The power-on reset circuitry is designed to remain active
under all conditions and will produce a valid output even
when V
(7µA typical) ensures continuous operation of the POR
circuit.
GND is the negative reference for all voltages. This
current that flows in the ground connection is very low
(35µA typical with the regulator enabled and 7µA typical
with the regulator disabled).
OUT
+
is the Power-On-Reset output pin (Active Low).
OUT
falls below the
CC
C
10µF
OUT
OUT
the regulator is disabled.
POR
is not present. A very low quiescent current
OUT
rises above the
GND
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falls below the
circuits. This ensures excellent start-up
uP Reset
V
3.3V/500mA
OUT
POR
OUT
POR
POR
threshold voltage
will also be used to provide
POR
will remain logic low. If it
threshold voltage
threshold voltage
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CMPWR160
POR
is
3