MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 71

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

(6)IRL Latch/Clear Register (IRLAT)
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 5
bit 4
bit 3 to bit 0
(7)IRC Mode Register (IMODE)
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 2
bit 1 to bit 0
17. DRAM controller
(1)DRAM Bank Configuration Register (DBANKR)
bit 31
bit 30 to bit 11 :Reserved [“0”Write, Don’t care for read]
bit 10 to bit 9
bit 8
bit 7
bit 6 to bit 4
bit 3 to bit 0
X:Don’t care
(2)DRAM Timing Register (DTIMR)
bit 31 to bit 5
bit 4
bit 3 to bit 2
bit 1
bit 0
bit
bit
bit
bit
31
31
ERR
31
31
:Reserved [“0”Write, Read"0"]
:IRL Clear [Wite only] (Clear
:IRL Latch [Read only] (RST
:Reserved [“0”Write, Read“0”]
:IRC Mode [IRCMD] (Disable
:Access Error [ERR] (Error
:DRAM Start Address [STADR] (RST
:Hyper Page Enable [HE] (Page Mode DRAM
:DRAM Type[TP] (4CAS-1WE= 0, 4WE -1CAS
:Column Address [COL] (RST
:Bank Size [BKSIZE] (RST
:Reserved [“0”Write, Don’t care for read]
:RAS#Precharge time specification bits [T
:RAS#Pulse width specification bit [T
(1 Cycle
:CAS#Pulse width specification bit [T
:RAS#Precharge width specification bit [T
00, 2 Cycle
Reserved
Reserved
Reserved
01, 3 Cycle
Reserved
1, No Error
0011)
1, Not Clear
0000)
00, Enable
011)
RASCBR
CAS
10, RST
01)
] (1 Cycle
RP
RPS
] at CBR Refresh
0, RST
] (1 Cycle
16 15
16 15
] at Self-Refresh (2 Cycle
01, RST
0)
11 10
0, EDO DRAM
1, RST
01)
STADR HE TP
0, 2 Cycle
X, “0”Write Clear)
0, 2 Cycle
00)
9
Reserved
0)
CS3#
CS3#
CS3#
8
CS3#
MB86830 Series
Reserved
1, RST
7
1, RST
5
1, RST
L, Address<9:2>
L, Address<9:2>
6
L, Address<9:2>
L, Address<9:2>
T
COL
RPS
0, 4 Cycle
4
1)
5
0)
4
CL
T
0)
3
4
RASCBR
3
3
2
BKSIZE
1, RST
2
T
IRL
1
CAS
0x08
0x09
0x06
IRCMD
0x05
1
T
0
0
RP
0
1)
0
71