SD60C31/P AUK [AUK corp], SD60C31/P Datasheet
SD60C31/P
Related parts for SD60C31/P
SD60C31/P Summary of contents
Page 1
... SD60C31 SD60C31 SD60C51 SD60C51 Outline Dimensions PLCC44 SD60C31/P, SD60C51 CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER Package Code Type NO. ...
Page 2
... SFR ROM Bus Four I/O Ports Control P0 P2 Address/Data - Figure 60C51L Block Diagram KSI-W001-000 SD60C31/P SD60C51 Timer 1 128 RAM Timer 0 Serial Port TxD RxD P1 P3 Unit °C ° ...
Page 3
... ALE/PROG 30 13 TxD/3.1 PSEN 29 14 INT0/P3.2 P2.7/A15 INT1/P3 T0/P3.4 16 P2.6/A14 27 17 T1/P3.5 P2.5/A13 26 P2.4/A12 25 P2.3/A11 24 P2.2/A10 23 P2.1/A9 22 P2.0/A8 21 KSI-W001-000 SD60C31/P SD60C51 44PLCC 34 PLCC44 Port 0 pins that have 1's P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 3 ...
Page 4
... RxD (Serial input port) 11 TxD (Serial output port) 12 INT0 (external interrupt 0) 13 INT1 (external interrupt (Timer 0 external input (Timer 1 external input (external data memory write strobe (external data memory read strobe) CC KSI-W001-000 SD60C31/P SD60C51/P Alternate Function permits Power- ...
Page 5
... Input to the inverting oscillator amplifier and input to the internal clock generator circuits PIN1, 12, 23, 34 (PLCC44) Non connection pins. XTAL2 : PIN 18 (DIP40), PIN 20(PLCC44) Output from the inverting oscillator amplifier the device executes from internal program memory unless CC KSI-W001-000 SD60C31/P SD60C51/P in order to enable the device SS 5 ...
Page 6
... The control bits for the reduced power modes are in the special function register PCON. Table Status of the external pins during Idle and power down modes. Program Mode memory Idle Internal Idle External Power down Internal Power down External SD60C31/P SD60C51/P XTAL2 30pF 30pF XTAL1 V ALE PSEN PORT Data 1 ...
Page 7
... OH I =-25 ㎂ =-10 ㎂ =-800 ㎂ =-300 ㎂ =-80 ㎂ =0.45V IN V =2V IN current to 0.45<V < See note1 pull-down test conditions. Minimum V CC KSI-W001-000 SD60C31/P SD60C51/P LIMITS MIN TYP. MAX 0.2V -0.5 0.1 0.2V 0 0.3 0. +0.5 CC 0 0.45 0.45 2.4 0.75V CC 0.9V CC 2.4 0.75V CC 0.9V ...
Page 8
... CLCH t 4 Fall time CHCL =0V) SS CLOCK MIN frequency : Speed 127 205 0 400 400 0 200 203 KSI-W001-000 SD60C31/P SD60C51/P 12MHz VARIABLE CLOCK MAX MIN 3.5 2t -40 CLCL t -55 CLCL t -35 CLCL 234 4t t -40 CLCL 3t -45 CLCL 145 3 CLCL ...
Page 9
... Figure 1. External Program Memory Read Cycle t LLDV t t LLWL RLRH t t LLAX RLDV t RHDX t RLAX DATA IN t AVWL t AVDV P2 A15 FROM DPH Figure 2. External Data Memory Read Cycle KSI-W001-000 SD60C31/P SD60C51/P t PXIZ A15 t WHLH t RHDZ FROM PCL A0 - A15 FROM PCH INSTR IN 9 ...
Page 10
... For timing purposes, a port is no longer floating when a 100mV change from load v oltage occurs, and begings -0.5 for a logic CC to float when a 100mV change from the loaded V lev el occurs. for a logic '0' IL KSI-W001-000 SD60C31/P SD60C51/P t WHLH t WHQX FROM PCL A0 - A15 FROM PCH t CHCX ...
Page 11
... FREQ Icc Valid only within frequency specifications of the device under test CLOCK SIGNAL Figure 9. I KSI-W001-000 SD60C31/P SD60C51/P MAX ACTIVE MODE TYP ACTIVE MODE MAX IDLE MODE TYP IDLE MODE 16MHz RST (NC) XTAL2 XTAL1 V SS ...
Page 12
... All other pins are disconnected 0 0. 0.1 0.45V 0. CHCL CLCX Tests in Active and Idle Modes 5㎱ CLCH CHCL RST (NC) XTAL2 XTAL1 V SS Test Condition, Power down Mode cc KSI-W001-000 SD60C31/P SD60C51/P t CHCX t CLCH t CLCL 5. ...