MSC2343257A-XXBS8 OKI [OKI electronic componets], MSC2343257A-XXBS8 Datasheet - Page 8

• Manufacturer Part Number: MSC2343257A-XXBS8
• Description: 4,194,304-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
• Manufacturer: OKI [OKI electronic componets]

MSC2343257A-xxBS8/DS8
Notes:
108
10. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
11. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight
2. The AC characteristics assume t
3. V
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
6. Operation within the t
7. t
8. t
9. t
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
Transition times (t
t
t
t
t
the open circuit condition and are not referenced to output voltage levels.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. CA0, CA1
and CA10 are not used. In a read cycle, if all internal bits are equal, the DQ pin will
indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low
level. The test mode is cleared and the memory device returned to its normal
operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh
cycle.
The 4M ¥ 32 module can be tested as an 1M ¥ 32 module in this test mode.
mode parameters are obtained by adding 5 ns to the normal read cycle values.
RCD
RCD
RAD
RAD
CEZ
CEZ
RCH
IH
(Min.) and V
(Max.), t
and t
(Max.) is specified as a reference point only. If t
(Max.) limit, access time is controlled by t
(Max.) is specified as a reference point only. If t
(Max.) limit, access time is controlled by t
or t
See ADDENDUM I for AC Timing Waveforms
RRH
REZ
REZ
must be satisfied for a read cycle.
must be satisfied for open circuit condition.
(Max.) and t
IL
T
) are measured between V
(Max.) are reference levels for measuring input timing signals.
RCD
RAD
(Max.) limit ensures that t
(Max.) limit ensures that t
WEZ
T
= 5 ns.
(Max.) define the time at which the output achieves
IH
CAC
AA
and V
.
.
RCD
RAD
RAC
RAC
IL
.
is greater than the specified
is greater than the specified
(Max.) can be met.
(Max.) can be met.
¡ Semiconductor