bu76292aguw ROHM Co. Ltd., bu76292aguw Datasheet - Page 3

• Manufacturer Part Number: bu76292aguw
• Description: Audio Interface + Video Driver + Back Up + Rtc Lsi
• Manufacturer: ROHM Co. Ltd.

◇Register map
◇Serial interface
Control commands are entered on the CSB, SCLK, and SDATA pins, outputted on the SOUT pin, using 4 line 16 bit serial input (MSB first).
The input cycle is started on the CSB falling edge, and each bit of data is read in on the SCLK rising edge.
The data is loaded to register on the CSB rising edge.
Address
0CH
0DH
1CH
1DH
00H
01H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0EH
0FH
10H
13H
17H
18H
19H
1AH
1BH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
41H
42H
43H
44H
45H
46H
50H
57H
（note） Do not write to the address except for the above.
Power control
Power control
Gain control
Gain control
Clock control
Clock control
Clock control
ALC control
ALC control
ALC control
Time control
Volume control
Filter control
Volume control
Volume control
Volume control
Video gain control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
RTC counter
RTC counter
RTC counter
RTC counter
RTC control
RTC control
Back up register
：
Back up register
SDATA
SOUT
SCLK
CSB
Register
“x”
R/W
Register Address
Control Data
R/W
MASTER
RC2MC1
DFMRP
FMCK1
ATMC1
DVOL7
DF0M1
DF1M1
DF2M1
DF3M1
DF4M1
REG63
DF0A7
DF0B7
DF1A7
DF1B7
DF2A7
DF2B7
DF3A7
DF3B7
DF4A7
DF4B7
RTC15
RTC23
RTC31
RTC７
REG7
RINI2
D7
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
COMENB
A4
MDALC1
RC2MC0
OLDFM
FMCK0
FRCK2
ATMC0
DVOL6
DF0M0
DF1M0
DF2M0
DF3M0
DF4M0
REG62
DF0A6
DF0B6
DF1A6
DF1B6
DF2A6
DF2B6
DF3A6
DF3B6
DF4A6
DF4B6
RTC14
RTC22
RTC30
PWSV
MLIM6
BFPD
RTC6
REG6
RINI1
“x”
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
A2
MDEVR1
SPVOL1
DF0A13
DF0B13
DF1A13
DF1B13
DF2A13
DF2B13
DF3A13
DF3B13
DF4A13
DF4B13
RCMC1
FRCK1
CVRG1
DVOL5
REG61
FBCK1
RTC13
RTC21
RTC29
MLIM5
DF0A5
DF0B5
DF1A5
DF1B5
DF2A5
DF2B5
DF3A5
DF3B5
DF4A5
DF4B5
A1
PWAP
FSSK
EVR5
REG5
RINI0
RTC5
ADA
D5
0
0
0
0
0
0
0
REV. B
A0
: A6 - A0
: D7 - D0
: READ/WRITE(“1” WRITE, “0” READ)
D7
D7
MDEVR0
DFMEN4
PWMRG
SPVOL0
DF0A12
DF0B12
DF1B12
DF2B12
DF3B12
DF4B12
RCMC0
DF1A12
DF2A12
DF3A12
DF4A12
CVRG0
FBCK0
FRCK0
DVOL4
REG60
MLIM4
DF0A4
DF0B4
DF1A4
DF1B4
DF2A4
DF2B4
DF3A4
DF3B4
DF4A4
DF4B4
RTC12
RTC20
RTC28
REG4
DLEN
EVR4
RTC4
PINI1
D6
D6
D4
0
0
0
0
0
0
0
D5
D5
D4
D4
DFMEN3
DF0A11
DF0B11
DF1A11
DF1B11
DF2A11
DF2B11
DF3A11
DF3B11
DF4A11
DF4B11
FMCO3
HPFR3
DVOL3
REG59
DIFGS
ATSP1
MLIM3
DF0A3
DF0B3
DF1A3
DF1B3
DF2A3
DF2B3
DF3A3
DF3B3
DF4A3
DF4B3
RTC11
RTC19
RTC27
PWVD
MDSP
MUSP
RCLM
REG3
EVR3
RTC3
SFS1
PINI0
D3
0
0
0
0
0
0
D3
D3
D2
D2
DFMEN2
MUBSP
DF0A10
DF0B10
DF1A10
DF1B10
DF2A10
DF2B10
DF3A10
DF3B10
DF4A10
DF4B10
HPFR2
DVOL2
REG58
D1
D1
ATSP0
MLIM2
BVOL2
DF0A2
DF0B2
DF1A2
DF1B2
DF2A2
DF2B2
DF3A2
DF3B2
DF4A2
DF4B2
RTC10
RTC18
RTC26
LGAIN
MCKO
MDPB
EVR2
RTC2
REG2
SFS0
DIF2
D2
0
0
0
0
0
0
0
D0
D0
DFMEN1
MGAIN1
“x”
MDREC
RCSP1
DVOL1
REG57
ATTO1
HPFR1
BVOL1
DF0A9
DF0B9
DF1B9
DF2B9
DF3B9
DF4B9
RTC17
RTC25
MLIM1
VGAIN
DF0A1
DF0B1
DF1A9
DF1A1
DF1B1
DF2A9
DF2A1
DF2B1
DF3A9
DF3A1
DF3B1
DF4A9
DF4A1
DF4B1
MULO
REG1
DVLT
EVR1
RTC1
RTC9
DIF1
DIV1
D1
0
0
0
0
0
DFMEN0
MGAIN0
MUDVL
MDDVL
MDPLL
RCSP0
CNTEN
HPFR0
DVOL0
BVOL0
REG56
ATTO0
MLIM0
DF0A8
DF0A0
DF0B8
DF0B0
DF1A8
DF1A0
DF1B8
DF1B0
DF2A8
DF2A0
DF2B8
DF2B0
DF3A8
DF3A0
DF3B8
DF3B0
DF4A8
DF4A0
DF4B8
DF4B0
RTC16
RTC24
REG0
EVRT
EVR0
RTC0
RTC8
DIF0
DIV0
ERR
D0
0
0
0
3/4