w364m72v-essb ETC-unknow, w364m72v-essb Datasheet - Page 12
w364m72v-essb
Manufacturer Part Number
w364m72v-essb
Description
64mx72 Synchronous Dram
Manufacturer
ETC-unknow
Datasheet
1.W364M72V-ESSB.pdf
(16 pages)
January 2005
Rev. 1
Parameter
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time (22)
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time (load) (26)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows) – Commercial, Industrial
Refresh period (8,192 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
White Electronic Designs
CL = 3 (10)
CL = 2 (10)
CL = 3
CL = 2
CL = 3
CL = 2
(23)
(24)
(NOTES 5, 6, 8, 9, 11)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CMH
CMS
t
t
t
OHN
t
t
t
CKH
CKS
t
t
t
RAS
RCD
REF
REF
RFC
t
RRD
XSR
OH
WR
AC
AC
AH
AS
CH
CL
CK
CK
DH
DS
HZ
HZ
RC
RP
t
LZ
T
12
1 CLK + 7ns
Min
1.8
0.3
10
13
50
70
20
70
20
20
15
80
1
2
3
3
1
2
1
2
1
2
1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
-100
120,000
Max
1.2
64
16
7
7
7
7
1 CLK + 7ns
W364M72V-XSBX
Min
1.8
0.3
10
50
68
20
70
20
20
15
80
1
2
3
3
8
1
2
1
2
1
2
1
3
-125
120,000
Max
64
16
1.2
6
6
6
6
ADVANCED
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
ns
ns