k7a803600a-16 Samsung Semiconductor, Inc., k7a803600a-16 Datasheet
k7a803600a-16
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k7a803600a-16 Summary of contents
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... K7A803600A K7A801800A Document Title 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History 0.0 Initial draft 1.0 1. Final spec Release. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. 256Kx36 & ...
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... LBO pin is DC operated and determines burst sequence(lin- ear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. -15 -14 -10 Unit The K7A803600A and K7A801800A are fabricated using 6.7 7 SAMSUNG s high performance CMOS technology and is available in a 100pin TQFP and 119BGA package. Multiple 3 ...
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... The pin 42 is reserved for address bit for the 16Mb . 256Kx36 & 512Kx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7A803600A(256Kx36) TQFP PIN NO. SYMBOL PIN NAME 32,33,34,35,36,37,43 V Power Supply(+3.3V) ...
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... K7A803600A K7A801800A PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ N.C. 6 N.C. 7 DQb 8 0 DQb SSQ V 11 DDQ 12 DQb 2 13 DQb DQb 18 4 DQb DDQ V 21 SSQ DQb 22 6 DQb 23 7 DQPb 24 N.C. 25 ...
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... K7A803600A K7A801800A 119BGA PACKAGE PIN CONFIGURATIONS K7A803600A(256Kx36 DDQ DQc DQPc E DQc DQc F V DQc DDQ G DQc DQc H DQc DQc DDQ DD K DQd DQd L DQd DQd M V DQd DDQ N DQd DQd P DQd DQPd ...
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... K7A803600A K7A801800A 119BGA PACKAGE PIN CONFIGURATIONS K7A801800A(512Kx18 DDQ DQb DQb DDQ G NC DQb H DQb DDQ DQb L DQb DQb DDQ N DQb DQPb DDQ Note : * A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired ...
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... K7A801800A FUNCTION DESCRIPTION The K7A803600A and K7A801800A are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. ...
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... K7A803600A K7A801800A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADSP ADSC ADV ...
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... K7A803600A K7A801800A PASS-THROUGH TRUTH TABLE PREVIOUS CYCLE OPERATION WRITE Write Cycle, All bytes All L Address=An-1, Data=Dn-1 Write Cycle, All bytes All L Address=An-1, Data=Dn-1 Write Cycle, All bytes All L Address=An-1, Data=Dn-1 Write Cycle, One byte One L Address=An-1, Data=Dn-1 Write Cycle, One byte ...
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... K7A803600A K7A801800A DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ Output Leakage Current I OL Operating Current Standby Current I SB1 I SB2 Output Low Voltage(3.3V I/ Output High Voltage(3.3V I/ Output Low Voltage(2.5V I/ Output High Voltage(2.5V I/ Input Low Voltage(3.3V I/O) ...
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... K7A803600A K7A801800A Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
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... K7A803600A K7A801800A 256Kx36 & 512Kx18 Synchronous SRAM - 12 - July 2000 Rev 1.0 ...
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... K7A803600A K7A801800A 256Kx36 & 512Kx18 Synchronous SRAM - 13 - July 2000 Rev 1.0 ...
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... K7A803600A K7A801800A 256Kx36 & 512Kx18 Synchronous SRAM - 14 - July 2000 Rev 1.0 ...
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... K7A803600A K7A801800A 256Kx36 & 512Kx18 Synchronous SRAM - 15 - July 2000 Rev 1.0 ...
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... K7A803600A K7A801800A 256Kx36 & 512Kx18 Synchronous SRAM - 16 - July 2000 Rev 1.0 ...
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... K7A803600A K7A801800A APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. Data Address A [0:18] CLK Microprocessor CLK ...
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... K7A803600A K7A801800A APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. Data Address A [0:19] CLK Microprocessor CLK ...
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... K7A803600A K7A801800A PACKAGE DIMENSIONS 100-TQFP-1420A 22.00 20.00 #1 0.65 256Kx36 & 512Kx18 Synchronous SRAM 0.30 0.20 16.00 0.30 14.00 0.20 (0.83) (0.58) 0.30 0.10 0.10 MAX 1.40 1.60 MAX 0.10 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 0.10 MAX 0.50 0.10 July 2000 Rev 1.0 ...
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... K7A803600A K7A801800A 119BGA PACKAGE DIMENSIONS 14.00 0.10 Indicator of Ball(1A) Location C1.00 0.60 0.10 12.50 0.10 256Kx36 & 512Kx18 Synchronous SRAM 22.00 0.10 20.50 0.10 C0.70 1.50REF Notes 0.60 0.10 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 Max. 3. PCB to Cavity Offset : 0.10 Max 1.27 1.27 0.750 0.15 July 2000 Rev 1.0 ...