k7a803600m Samsung Semiconductor, Inc., k7a803600m Datasheet - Page 17

• Manufacturer Part Number: k7a803600m
• Description: 256kx36 & 512kx18 Synchronous Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7A803600M
K7A801800M
The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
APPLICATION INFORMATION
DEPTH EXPANSION
INTERLEAVE READ TIMING
Microprocessor
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
ADDRESS
[0:n]
WRITE
CS
A
ADV
OE
Data Out
(Bank 0)
Data Out
(Bank 1)
n+1
1
Address
t
Data
ADS
SS
CLK
*Notes : n = 14 32K depth ,
A1
t
SH
t
WS
t
LZOE
16 128K depth ,
18 512K depth
Bank 0 is selected by CS
A
[0:18]
t
ADVS
t
t
WH
OE
CLK
Q1-1
(Refer to non-interleave write timing for interleave write timing)
Cache
Controller
Address
t
ADVH
15 64K depth
17 256K depth
2
, and Bank 1 deselected by CS
Q1-2
256Kx36 & 512Kx18 Synchronous SRAM
A
Q1-3
- 17 -
[18]
t
CSS
t
AS
A
Q1-4
CS
CS
CLK
ADSC
WEx
OE
CS
[0:17]
A2
2
Address Data
t
ADV
HZC
2
2
1
t
t
AH
CSH
t
LZC
t
CD
256Kx36
SPB
SRAM
(Bank 0)
ADSP
Bank 0 is deselected by CS
I/O
Q2-1
A
[0:71]
[18]
Q2-2
2
, and Bank 1 selected by CS
A
Don t Care
[0:17]
CS
CS
CLK
ADSC
WEx
OE
CS
Address Data
ADV
2
2
1
Q2-3
256Kx36
SPB
SRAM
(Bank 1)
March 2000
ADSP
Undefined
Rev 6.0
Q2-4
2