89ttm553 Integrated Device Technology, 89ttm553 Datasheet - Page 15

• Manufacturer Part Number: 89ttm553
• Description: Traffic Manager Co-processing Engine
• Manufacturer: Integrated Device Technology

89TTM553 Reset Sequence
89TTM553 Reset Sequence
89TTM553 Reset Sequence
89TTM553 Reset Sequence
section describes the reset sequence for the 89TTM553 device.
PLL_CFG_OVR pin controls this feature. When left high, the PLL will determine its clock frequency by sampling these values on the ZBus pins. The
feature is not necessary if the default clock frequencies are desired. (The default frequency for the core clock is 133 MHz when a 100 MHz clock refer-
ence is used.) When default frequencies are desired, the PLL_CFG_OVR should be held low and it is not necessary to drive the ZBus data and parity
lines during the reset.
Core
Core P P P PLL Frequency Setting
Core
Core
properly. Note that the setting is based on a 100MHz reference input clock (PLL_SYS_REFCLK pin).
IDT 89TTM553
A PLL reset sequence must be followed when resetting the 89TTM553 to ensure that clocks are stable when the chip comes out of reset. This
The 89TTM553 uses data presented on the ZBus data and parity pins to determine the clock frequencies when the chip is in reset. The
Following is the summary of the reset sequence:
1. Assert chip reset.
2. Drive LOR (latch on reset) values on ZBus (described below) and enable configuration override on all PLLs. (Configuration override remains
3. Reset PLLs.
4. Release reset on PLLs.
5. Release chip reset.
6. Release LOR value on ZBus.
The following values must be driven on ZBUS_AD[ ] and ZBUS_PRTY before the reset sequences in order to set the chip operation frequency
ON forever).
ZB_PRTY[1:0] = 0x3, must be driven “LOW” for the entire reset sequence cycles
ZB_AD[31:16], and ZB_AD[15:0] = bits are set as:
LL Frequency Setting
LL Frequency Setting
LL Frequency Setting
0x154F =
0x1527 =
0x153a =
0x1526 =
0x1538 =
0x1525 =
Core/system clock frequency
187.50MHz
175.00MHz
166.67MHz
150.00MHz
133.33MHz
125.00MHz
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March 3, 2005