k7r321884c Samsung Semiconductor, Inc., k7r321884c Datasheet - Page 8

• Manufacturer Part Number: k7r321884c
• Description: 1mx36-bit, 2mx18 And 4mx9-bit Qdr Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

Single Clock Mode
Depth Expansion
Programmable Impedance Output Buffer Operation
Echo clock operation
K7R323684C
K7R321884C
K7R320984C
Power-Up/Power-Down Supply Voltage Sequencing
The K7R323684C, K7R321884C and K7R320984C can be operated with the single clock pair K and K, instead of C or C for output
clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high dur-
ing operation. After power up, this device can’t change to or from single clock mode. System flight time and clock skew could not be
compensated in this mode.
Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read
and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed.
Clock Consideration
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
The value of RQ (within 15%) is five times the output impedance desired. For example, 250
of 50
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates
are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn-
chronized with internal data output. Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.
The following power-up supply voltage application is recommended: V
simultaneously, as long as V
removal sequence is recommended: V
does not exceed V
K7R323684C, K7R321884C and K7R320984C utilizes internal DLL (Delay-Locked Loops) for maximum output data valid window. It
can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Ω
.
DD
by more than 0.5V during power-down.
DDQ
does not exceed V
IN
, V
REF
, V
DDQ
DD
, V
by more than 0.5V during power-up. The following power-down supply voltage
1Mx36, 2Mx18 & 4Mx9 QDR
DD
, V
SS
- 8 -
. V
DD
SS
and V
, V
DD
DDQ
, V
DDQ
can be removed simultaneously, as long as V
, V
REF
, then V
Ω
resistor will give an output impedance
SS
Rev. 1.1 August 2006
through a precision resistor(RQ).
IN
. V
DD
and V
TM
II b4 SRAM
DDQ
can be applied
DDQ