adc-hz-883 C&D Technologies., adc-hz-883 Datasheet - Page 2

• Manufacturer Part Number: adc-hz-883
• Description: 12-bit, 8 And 20?sec Analog-to-digital Converters
• Manufacturer: C&D Technologies.

ADC-HX, ADC-HZ
ABSOLUTE MAXIMUM RATINGS
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C and ±15V and +5V supplies unless otherwise noted)
PARAMETERS
+15V Supply, Pin 28
–15V Supply, Pin 31
+5V Supply, Pin 16
Digital Inputs, Pins 14, 21
Analog Inputs, Pins 24, 25
Buffer Input, Pin 30
Lead Temperature (10 seconds)
INPUTS
Analog Input Ranges
Input Impedance
Input Impedance with Buffer
Input Bias Current of Buffer
Start Conversion
PERFORMANCE
Resolution
Nonlinearity
Differential Nonlinearity
Accuracy Error
Temperature Coefficient
Diff. Nonlinearity Tempco
No Missing Codes
Conversion Time
Buffer Settling Time (10V step)
Power Supply Rejection
OUTPUTS
Parallel Output Data
Unipolar Coding
Bipolar Coding
Serial Output Data
End of Conversion (Status)
Clock Output
Internal Reference
Reference Tempco
External Reference Current
Unipolar
Bipolar
Gain (before adjustment)
Zero, Unipolar (before adj.)
Offset, Bipolar (before adj.)
Gain
Zero, Unipolar
Offset, Bipolar
12 Bits
10 Bits
8 Bits
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1194 (U.S.A.) Tel: [phone] Fax: [phone] • For immediate assistance 800-233-2765
0 to +5V, 0 to +10V
±2.5V, ±5V, ±10V
2.5k (0 to +5V, ±2.5V)
5k (0 to +10V, ±5V)
10k (±10V)
50 megohms
125nA typical, 250nA max.
+2V min. to +5.5V max. positive pulse with dur-
ation of 100ns min. Rise and fall times <30ns.
Logic "1" to "0" transition resets converter and
initiates next conversion. Loading: 2 TTL loads.
12 bits
±1/2LSB max.
±3/4LSB max.
±0.2%
±0.1% of FSR
±0.2% of FSR
±20ppm/°C max.
±5ppm/°C of FSR max.
±10ppm/°C of FSR max.
±2ppm/°C of FSR max.
Over opererating temperature range
20µs max.
15µs max.
10µs max.
3µs to ±0.01%
±0.004%/% supply max.
12 parallel lines of data held until next
conversion command.
V
V
Complementary binary
Complementary offset binary
Complementary two’s complement
NRZ successive decision pulses out, MSB first.
Compl. binary or compl. offset binary coding.
Conversion status signal. Output is logic "1"
during reset and conversion and logic "0"
when conversion complete.
Train of positive going +5V 100ns pulses.
600kHz for ADC-HX and 1.5MHz for
ADC-HZ (pin 17 grounded).
+6.3V
±20ppm/°C max.
2.5mA max.
OUT
OUT
ADC-HX12B
("0") +0.4V
("1") +2.4V
LIMITS
±5.5
+18
±25
±15
–18
300
+7
ADC-HZ12B
8µs max.
6µs max.
4µs max.
UNITS
Volts
Volts
Volts
Volts
Volts
Volts
°C
TECHNICAL NOTES
1. It is recommended that the ±15V power input pins both be
2. DIGITAL COMMON (pin 15) and ANALOG COMMON
3. External adjustment of zero or offset and gain are made by
4. Short-cycled operation results in shorter conversion times
POWER REQUIREMENTS
Power Supply Voltages
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range, Case
Storage Temperature Range
Package Type
Weight
Thermal Impedance
Footnotes:
bypassed to ground with a 0.01µF ceramic capacitor in
parallel with a 1µF electrolytic capacitor and the +5V power
input pin be bypassed to ground with a 10µF electrolytic
capacitor as shown in the connection diagrams. In addition,
GAIN ADJUST (pin 27) should be bypassed to ground with
a 0.01µF ceramic capacitor. These precautions will assure
noise free operation of the converter.
(pin 26) are not connected together internally, and therefore
must be connected as directly as possible externally. It is
recommended that a ground plane be run underneath the
case between the two commons. Analog ground and ±15V
power ground should be run to pin 26 whereas digital
ground and +5V ground should be run to pin 15.
using trimming potentiometers connected as shown in the
connection diagrams. The potentiometer values can be
between 10k and 100k Ohms and should be 100ppm/°C
cermet types. The trimming pots should be located as close
as possible to the converter to avoid noise pickup. In some
cases, for example 8-bit short-cycled operation, external
adjustment may not be necessary.
when the conversion is truncated to less than 12 bits. This
is done by connecting SHORT CYCLE (pin 14) to the
output bit following the last bit desired. For example, for an
8-bit conversion, pin 14 is connected to the bit 9 output.
Maximum conversion times are given for short-cycled
conversions of 8 or 10 bits. In these two cases, the clock
rate is accelerated by connecting the CLOCK RATE adjust
(pin 17) to +5V (10 bits) or +15V (8 bits). The clock rate
should not be arbitrarily speeded up to exceed the
maximum conversion rate at a given resolution, as missing
codes will result.
Adjustable to zero.
FSR is full scale range and is 10V for 0 to +10V or ±5V inputs and 20V for
±10V input, etc.
Without buffer amplifier used. ADC-HZ may require external adjustment
of clock rate.
Short cycled operation.
All digital outputs can drive 2 TTL loads.
JC
JA
+15V ±0.5V at +20mA
–15V ±0.5V at –25mA
+5V ±0.25V at +85mA
0 to +70°C or –55 to +125°C
–65 to +150°C
32-pin ceramic TDIP
0.5 ounces (14 grams)
6°C/W
30°C/W
®
®