u3745bm ATMEL Corporation, u3745bm Datasheet - Page 15

• Manufacturer Part Number: u3745bm
• Description: Receiver
• Manufacturer: ATMEL Corporation

Figure 12. Timing Diagram for Failed Bit Check (condition: CV_Lim ³ Lim_max)
Duration of the Bit Check
Receiving Mode
Digital Signal Processing
4663A–RKE–06/03
Bit check Counter
Dem_out
Bit check
Enable IC
(Lim_min = 14, Lim_max = 24 )
Startup Mode
0
1
If no transmitter signal is present during the bit check, the output of the demodulator
delivers random signals. The bit check is a statistical process and T
each check. Therefore, an average value for T
Characteristics”. T
baudrate range causes a lower value for T
in polling mode.
In the presence of a valid transmitter signal, T
that signal, f
thereby results in a longer period for T
preburst T
If the bit check has been successful for all bits specified by N
switches to receiving mode. According to Figure 9, the internal data signal is switched to
pin DATA in that case. A connected microcontroller can be woken up by the negative
edge at pin DATA. The receiver stays in that condition until it is switched back to polling
mode explicitly.
The data from the demodulator (Dem_out) is digitally processed in different ways and as
a result converted into the output signal data. This processing depends on the selected
baud rate range (BR_Range). Figure 13 illustrates how Dem_out is synchronized by the
extended clock cycle T
change its state only after T
signal as a result is always an integral multiple of T
The minimum time period between two edges of the data signal is limited to
t
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T
ceding edge-to-edge time interval t
specified bit check limits, the following level is frozen for the time period
T
relevant stable time period.
The maximum time period for DATA to be low is limited to T
ensures a finite response time during programming or switching off the receiver via pin
DATA. T
transmitter data stream. Figure 15 gives an example where Dem_out remains low after
the receiver has switched to receiving mode.
ee
DATA_min
2 3 4 5 6
³ T
DATA_min
DATA_L_max
= tmin1, in case of t
Preburst
7
Sig
1
. This implies an efficient suppression of spikes at the DATA output. At the
2
and the count of the checked bits, N
.
3
Bitcheck
4 5
Bitcheck Mode
is thereby longer than the maximum time period indicated by the
6 7 8 9
XClk
depends on the selected baud rate range and on T
. This clock is also used for the bit check counter. Data can
XClk
ee
10
1/2 Bit
11 12
being outside that bit check limits T
elapsed. The edge-to-edge time period t
13 14 15 16 17 18 19
ee
as illustrated in Figure 14. If t
Bitcheck
DATA_min
Bitcheck
requiring a higher value for the transmitter
Bitcheck
Bit check failed (CV_Lim = Lim_max )
Bitcheck
20
resulting in lower current consumption
21 22 23 24
is to some extent affected by the pre-
XClk
Bitcheck
is dependant on the frequency of
.
is given in the section “Electrical
. A higher value for N
DATA_L_max
DATA_min
Bitcheck
Sleep Mode
ee
U3745BM
0
is in between the
Bitcheck
. This function
, the receiver
ee
= tmin2 is the
Clk
of the Data
varies for
. A higher
Bitcheck
15