ta1383afg TOSHIBA Semiconductor CORPORATION, ta1383afg Datasheet - Page 10

• Manufacturer Part Number: ta1383afg
• Description: Ntsc Chroma Decoder, Multi-point Scan Sync Processor, H/v Frequency Counter Ic For Color Tv
• Manufacturer: TOSHIBA Semiconductor CORPORATION

525I-SEP
MATRIX SW
BANDWIDTH
V-MODE
TEST
GAIN SW
HD-POL
VD-POL
C-TRAP
HD POSI
Signal
Switches 525I SEP Mode
Switches matrix.
Note: Set this function together with INPUT SW, H/V FREQUENCY for each
Switches bandwidth limiting filter (ADC pre-filter).
Switches vertical sync playback mode.
Note 1: Setting 0 is valid only for standard signals. For other signals, set to Direct
Note 2: Set this register to (1) except inputting the NTSC and 525I composite
Shipment Test Mode. When TEST = 01 and H/V FREQ = 111, V-pull-in range is
expanded (Refer to H/V FREQ function explanation). In other case, set to 00.
Switches output gain.
Switches HD output polarity.
Switches VD output polarity.
Switches chroma trap.
Adjusts HD output phase.
Note: Sync center is based on 33.75 kHz/3-level sync.
Switches H-SEP Mode. (Countermeasure ghost signal)
Sets I/O signal format for input pins (28, 29, and 30) and output pins (22, 23,
and 24).
Sets bandwidth of bandwidth limiting filter and image mute.
Switches VD OUT (pin 15) sync playback mode.
Sets output amp gain for pins 22, 23, and 24.
Sets HD OUT (pin 17) polarity.
Sets VD OUT (pin 15) polarity.
Switches chroma trap for image signals input to pins 2 and 4.
Sets output phase of HD OUT (pin 17).
0: ON
1: OFF
00: MODE-1 (YC1/YC2 → YCbCr, Y3/CbCr → YCbCr, RGB → YCbCr)
01: MODE-2 (YC1/YC2 → YCbCr, Y3/PbPr → YCbCr, RGB → YCbCr)
10: MODE-3 (YC1/YC2 → YPbPr, Y3/CbCr → YPbPr, RGB → YPbPr)
11: MODE-4 (YC1/YC2 → YPbPr, Y3/PbPr → YPbPr, RGB → YPbPr)
00: OFF (through)
01: Filter 1 (Y: 10.3 MHz/−3dB, Cb/Cr: 4.2 MHz/−3dB)
10: Filter 2 (Y: 14.6 MHz/−3dB, Cb/Cr: 6.5 MHz/−3dB)
11: Image mute (Y: −20IRE, CbCr: 0IRE)
0: PLL Mode for standard signals
0: +6dB
0: Positive polarity
0: Positive polarity
0: OFF
0000: 800 ns (2.7% of H cycle) ahead of sync center
1111: Sync center
input signal.
Automatically controls that H-SEP level does not go higher than V-SEP
level, the initial value is 40%.
Sync Mode.
In PLL Mode for standard signals, VD output starts with 4-µs delay in
relation to V-SYNC.
For other signals, 0.25-H delay.
sync format.
1: ON
1: 0dB
1: Negative polarity
1: Negative polarity
Function
10
1: Direct Sync Mode
Power-On Initial Value
TA1383AFG
PLL for standard
Positive polarity
Positive polarity
2005-09-05
signals
(0000)
OFF
OFF
OFF
(00)
(00)
(00)
0dB
(1)
(0)
(1)
(0)
(0)
(0)