wjce6353882206 Intel Corporation, wjce6353882206 Datasheet
wjce6353882206
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wjce6353882206 Summary of contents
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... Novel RF level detect facility via a separate ADC Intel Corporation Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Ordering Information DJCE6353 882077 ...
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... Users have access to all the relevant signal quality information, including input signal power level, signal-to-noise ratio, pre-Viterbi BER, post-Viterbi BER, and the uncorrectable block counts. The error rate monitoring periods are programmable over a wide range. The device is packaged 64-pin LQFP and is very low power. CE6353 2 Intel Corporation Data Sheet ...
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... Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Absolute Maximum Ratings 4.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.1 Selection of External Components 4.4.1.1 Loop Gain Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1.2 List of Equation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1.3 Calculating Crystal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.1.4 Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.1.5 Oscillator/Clock Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CE6353 Table of Contents 3 Intel Corporation Data Sheet ...
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... Figure 6 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7 - MPEG Output Data Waveforms Figure 8 - MPEG Timing - MOCLKINV = Figure 9 - MPEG Timing - MOCLKINV = Figure 10 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11 - External Clocking via AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CE6353 List of Figures 4 Intel Corporation Data Sheet ...
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... Table 1 - Pin Names - numeric Table 2 - Pin Names - alphabetical order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3 - Timing of 2-Wire Bus CE6353 List of Tables 5 Intel Corporation Data Sheet ...
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... Pin & Package Details 1.1 Pin Outline CE6353 Figure 2 - Pin Outline 6 Intel Corporation Data Sheet ...
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... Table 1 - Pin Names - numeric Function Pin Function 43 PLLTEST 6 PLLVdd 49 RESET 50 RFLEV 51 SADD0 52 SADD1 53 N/C 56 N/C 57 N/C 58 SLEEP 63 SMTEST 61 STATUS Table 2 - Pin Names - alphabetical order 7 Intel Corporation Data Sheet Pin Function 49 MDO0 50 MDO1 51 MDO2 52 MDO3 53 MDO4 54 Vdd 55 Vss 56 MDO5 57 MDO6 58 MDO7 59 CVdd 60 Vss 61 MOCLK ...
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... Serial address set I Production test (only set low) I Serial clock tuner I/O Serial data tuner I/O Primary AGC O Secondary AGC I/O General purpose I/O I/O Device reset I Crystal oscillator mode I PLL analog test O 8 Intel Corporation Data Sheet Vss 55 Vss 60 XTI 23 XTO 24 Type 3.3 1 3.3 1 CMOS Tristate 3 ...
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... AVdd 29, 32 AGnd 33 Vdd CE6353 Pin Description I/O positive input I negative input I RF level I PLL supply S S Core logic power S I/O ring power S Core and I/O ground S ADC analog supply S S 2nd ADC supply S 9 Intel Corporation Data Sheet Type V mA 1.8 0 1.8 3.3 0 1.8 0 3.3 ...
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... Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting intervals of these are programmable over a very wide range. CE6353 Figure 3 - OFDM Demodulator Diagram 10 Intel Corporation Data Sheet ...
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... Slope control bits have been provided for the AGCs and these have to be set correctly depending on the gain-versus-voltage slope of the gain control amplifiers. CE6353 Figure 4 - FEC Block Diagram 11 Intel Corporation Data Sheet ...
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... The FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT. It then uses either FFT to transform the data from the time domain to the frequency domain. An extremely hardware-efficient and highly accurate algorithm has been used for this purpose. CE6353 12 Intel Corporation Data Sheet ...
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... The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de- interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions to the FEC in the original order. CE6353 13 Intel Corporation Data Sheet ...
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... MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the CE6353 with a clock provided by the user. CE6353 14 Intel Corporation Data Sheet A trace-back This ...
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... The CE6353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. See register GPP_CTL address 0x8C. Master control mode is selected by setting register SCAN_CTL (0x62) [b3 The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2. CE6353 ADDR[3] ADDR[2] ADDR[1] SADD[1] SADD[0] VDD VDD VDD 15 Intel Corporation Data Sheet ...
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... A S DEVICE R A DATA ADDRESS (reg n) t LOW HD;DAT HIGH SU;DAT HD;STA Figure 5 - Primary 2-Wire Bus Timing 16 Intel Corporation Data Sheet W Write (= 0) R Read (= 1) NA NOT Acknowledge RADD Register Address DATA NA P (reg n+ SU;STO SU;STA ...
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... The rise time depends on the external bus pull up resistor. Loading prevents full speed operation. CE6353 Symbol f CLK t BUFF t HD;STA t LOW t HIGH t SU;STA t HD;DAT t SU;DAT SU;STO Table 3 - Timing of 2-Wire Bus 17 Intel Corporation Data Sheet Value Unit Min. Max 400 kHz 200 ns 200 ns 1300 ns 600 ns 200 ns 100 ns 100 ns 2 note ns ...
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... CE6353 188 byte packet output 184 Transport packet bytes 4 bytes MDO[0] 18 Intel Corporation Data Sheet 1st byte 2nd byte ...
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... Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80 Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10 MOCLK frequency = 45.06 MHz. CE6353 188 byte packet n Tp Figure 7 - MPEG Output Data Waveforms o C, Output load = 10pF Output load = 10pF. 19 Intel Corporation Data Sheet 1st byte packet n+1 Ti ...
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... The hold time is better when MOCLKINV = 1, therefore this should be used if possible. MOCLK MDO } MOSTRT MOVAL BKERRB BKERR CE6353 Units Minimum 1.0 10 Figure 8 - MPEG Timing - MOCLKINV = 1 Delay conditions Units Minimum 1.0 20 Figure 9 - MPEG Timing - MOCLKINV = 0 20 Intel Corporation Data Sheet ...
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... CVDD 1.62 1 periphery IDD P core IDD C XTI 16.00 4 fCLK -10 Symbol Min. Max. VDD -0.3 +3.6 CVDD -0.3 +2.0 VI -0.3 5.5 VI -0.3 VDD + 0.3 VO -0.3 5.5 VO -0.3 VDD + 0.3 TSTG -55 150 TOP - 125 21 Intel Corporation Data Sheet Typ. Max. Units 3.3 3 1.8 1. 170 mA 20.48 25.00 MHz 400 kHz 80 qC Unit ...
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... MICLK, SADD(4:0) VIH SLEEP, OSCMODE GPP(3:0), CLK1, VIH DATA1, RESET All inputs VIL SLEEP, SMTEST, MICLK, CLK1, OSCMODE SADD(4:0), DATA1, GPP(3:0) 20.4800 MHz ± 150 ppm ± 200 ppm 27 pF 0.4 mW max < Intel Corporation Data Sheet Min. Typ. Max. Unit 3.0 3.3 3.6 V 1.62 1.8 1.98 V 170 mA 300 PA 2.4 V ...
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... V operation -typical Rf 2 internal feedback resistor ESR maximum equivalent series resistance of crystal - given by crystal manufacturer (:) f fundamental frequency of crystal (Hz) CE6353 XTI XT0 XTI C1 C2 Figure 10 - Crystal Oscillator Circuit + out Intel Corporation Data Sheet OSCMODE ...
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... L does not fall outside the crystal pulling range or the circuit may fail to start the crystal manufacturer who can then cut a crystal to order which will L 24 Intel Corporation Data Sheet = out ...
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... Vpp must be >100 mV recommended that differential clock signals have VCM = 1.0V. For Vpp > 400 mV a resistor of >390 : in series with XTI or XTO may be required to limit the current taken from or supplied to the clock sources. CE6353 XTO XTI 36k 100k 10nF 22k 10nF 25 Intel Corporation Data Sheet Vdd OSCMODE ...
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... Application Circuit CE6353 Figure 12 - Typical Application Circuit 26 Intel Corporation Data Sheet ...