ax5051 AXSEM, ax5051 Datasheet - Page 26

• Manufacturer Part Number: ax5051
• Description: Ax5051 Radio
• Manufacturer: AXSEM

26
Note: HDLC mode follows High-Level Data Link Control (HDLC, ISO 13239) protocol.
Circuit Description
HDLC Mode
HDLC Mode is the main framing mode of the AX5051. In this mode, the
automatic packet delimiting, and optional packet correctness check by inserting and
checking a cyclic redundancy check (CRC) field.
The packet structure is given in the following table.
Flag
8 bit
HDLC packets are delimited with flag sequences of content 0x7E.
In
(FCS) can be programmed to be CRC-CCITT, CRC-16 or CRC-32.
The receiver checks the CRC, the result can be retrieved from the FIFO, the CRC is
appended to the received data.
For details on implementing a HDLC communication see the
RAW Mode
In Raw mode, the
simply serialises transmit bytes and de-serializes the received bit-stream and groups it into
bytes.
This mode is ideal for implementing legacy protocols in software.
RAW Mode with Preamble Match
Raw mode with preamble match is similar to raw mode. In this mode, however, the receiver
does not receive anything until it detects a user programmable bit pattern (called the
preamble) in the receive bit-stream. When it detects the preamble, it aligns the de-
serialization to it.
The preamble can be between 4 and 32 bits long.
Version 1.6
AX5051
Address
8 bit
the meaning of address and control is user defined. The Frame Check Sequence
8 or 16 bit
Control
AX5051
does not perform any packet delimiting or byte synchronization. It
Information
Variable length, 0 or more bits in multiples of 8
AX5051
FCS
16 / 32 bit
Programming Manual.
AX5051
Datasheet AX5051
(Optional Flag)
8 bit
performs