qh25f320s33b8 Numonyx, qh25f320s33b8 Datasheet - Page 13

• Manufacturer Part Number: qh25f320s33b8
• Description: Numonyx? Serial Flash Memory S33
• Manufacturer: Numonyx

Numonyx™ Serial Flash Memory (S33)
4.3
Table 2:
December 2007
Order Number: 314822-03
Symbol
HOLD#
VCC
VSS
W#
S#
Q
C
D
Signal Descriptions
Output
Signal Descriptions
Power
Power
Type
Input
Input
Input
Input
Input
SPI Clock: Provides the timing of the SPI interface. OP codes, addresses, and data are latched in
on the rising edge. SPI output data transitions after the falling edge.
SPI Data Input: Shifts all data (including OP codes, Address Bytes, as well as Data Bytes) into the
device. All data is clocked in on the rising edge of “C”, starting with the MSB. The rising edge input
applies to Modes 0 & 3 as depicted in
Modes” on page 24
SPI Data Output: Shifts all data out of the device. All output data is clocked out after the falling
edge of “C”, starting with the MSB. The falling edge output applies to Modes 0 & 3 as depicted in
Figure 12, “Supported SPI Bus Operation Modes” on page 24
SPI Select: Falling S# edge triggers command writes to the SPI interface. Rising S# edge
completes (or terminates) the SPI command cycle. When S# is high, “Q” is at high-Z.
SPI HOLD: Internally freezes the Synchronization Clock and sets “Q” to high-Z. To enter the Hold
condition, S# must be low. Refer to
details.
Write Protect: Enables write protection. Refer to
Power Supply: Source voltage. Writes to the flash array are inhibited when V
at invalid V
Ground: Connect to system ground. Do not float VSS.
CC
should not be attempted.
.
Section 8.1.2, “The Hold State” on page 24
Figure 12, “Supported SPI Bus Operation
Name and Function
Table 18 on page 32
for details.
CC
.
≤ V
LKO
. Operations
Datasheet
for
13