cav24c02 ON Semiconductor, cav24c02 Datasheet - Page 6

• Manufacturer Part Number: cav24c02
• Description: 2-kb, 4-kb, 8-kb, And 16-kb I2c Cmos Serial Eeprom
• Manufacturer: ON Semiconductor

Byte Write
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAV24Cxx. After receiving another
acknowledge from the Slave, the Master transmits the data
byte to be written into the addressed memory location. The
CAV24Cxx device will acknowledge the data byte and the
Master generates the STOP condition, at which time the
device begins its internal Write cycle to nonvolatile memory
(Figure 6). While this internal cycle is in progress (t
SDA output will be tri−stated and the CAV24Cxx will not
respond to any request from the Master device (Figure 7).
Page Write
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAV24Cxx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
In Byte Write mode, the Master sends the START
The CAV24Cxx writes up to 16 bytes of data in a single
BUS ACTIVITY:
MASTER
SLAVE
S
R
S
T
A
T
Figure 6. Byte Write Sequence
ADDRESS
SLAVE
WRITE OPERATIONS
WR
http://onsemi.com
), the
A
C
K
6
ADDRESS
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAV24Cxx in a single
write cycle.
Acknowledge Polling
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAV24Cxx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAV24Cxx is still busy
with the write operation, NoACK will be returned. If the
CAV24Cxx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
Hardware Write Protection
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAV24Cxx. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAV24Cxx will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
a
BYTE
7
The acknowledge (ACK) polling routine can be used to
With the WP pin held HIGH, the entire memory is
The CAV24Cxx is shipped erased, i.e., all bytes are FFh.
− a
0
C
A
K
d
BYTE
DATA
7
− d
0
A
C
K
P
O
S
T
P