msm514400d Oki Semiconductor, msm514400d Datasheet - Page 8

• Manufacturer Part Number: msm514400d
• Description: 1,048,576-word ? 4-bit Dynamic Ram Fast Page Mode Type
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Notes:
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight
2. The AC characteristics assume t
3. V
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
6. Operation within the t
7. t
8. t
9. t
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
Transition times (t
t
t
t
t
circuit condition and are not referenced to output voltage levels.
included in the data sheet as electrical characteristics only. If t
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t
t
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
RCD
RCD
RAD
RAD
OFF
RCH
WCS
AWD
IH
(Min.) and V
, t
(Max.) and t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
(Max.) is specified as a reference point only. If t
(Max.) limit, then the access time is controlled by t
or t
CWD
t
AWD
RRH
, t
RWD
must be satisfied for a read cycle.
(Min.) and t
, t
OEZ
IL
T
AWD
) are measured between V
(Max.) are reference levels for measuring input timing signals.
(Max.) define the time at which the output achieves the open
RCD
RAD
and t
CPWD
(Max.) limit ensures that t
(Max.) limit ensures that t
CPWD
T
t
= 5 ns.
CPWD
are not restrictive operating parameters. They are
(Min.), then the cycle is a read modify write
CWD
IH
and V
t
CWD
RCD
RAD
RAC
RAC
IL
CAC
AA
(Min.) , t
.
is greater than the specified
is greater than the specified
(Max.) can be met.
(Max.) can be met.
.
.
WCS
MSM514400D/DL
RWD
t
WCS
t
RWD
(Min.), then
(Min.),
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