rsc-4128 ETC-unknow, rsc-4128 Datasheet - Page 18

• Manufacturer Part Number: rsc-4128
• Description: Speech Recognition Processor
• Manufacturer: ETC-unknow

RSC-4128
Access of external ROM space is always controlled by these wait state bits. Internal ROM space and all external
R/W space accesses may also controlled by these bits, unless otherwise selected by bits in the clock extension
register (register D6, “clkExt”) The internal RAMs always operate with zero wait states.
Register D6 provides for extended control of some clocks derived from OSC1 for producing additional timer scaling
or specialized wait states. When Bit 5 is set, it overrides the “bank” register control of wait states during MOVX
instructions which access external read/write memory (register D2.Bit4=1), and forces a fixed value of 4 wait states
(nominal 350ns access). When Bit 7 is set, it overrides the “bank” register control of wait states during internal
ROM accesses and forces zero wait states.
accommodated within one application.
Bit 5
Bit 6
Bit 7
* MOVX accessing external read-write memory (“rw”; register D2.Bit4=1).
*MOVX instructions will have the number of wait states selected by register FC.Bits[7:5], unless register D2.Bit4
and register D6.Bit5 are set, in which case the number of wait states is fixed at 4.
18
Instruction
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
POP
PUSH
MOVY
MOVY
MOVD
Opcode
0: Certain MOVX* instructions use the Wait State divisor in register FC.Bits[7:5]
1:Certain MOVX* use fixed 4 Wait States (nominal 350nsec access)
0: MT timer clock is disabled
1: MT timer clock I s enabled
0: Accesses to internal ROM use the Wait State divisor set in register 0FCh[7:5]
1: Accesses to internal ROM use selected CLK (no wait states)
Cleared by reset.
Cleared by reset
Cleared by reset
1A
1B
1C
10
11
12
13
14
15
16
17
18
19
Operand 1
dest
@dest
dest
dest
dest
@dest
dest
@dest
dest
@dest--
dest
@dest
dest_pair
Operand 2
Source
Source
@source
#immed
@source
Source
@source
Source
@++source
Source
@source
source
source_pair
Using these controls, various memory access speeds may be
P/N 80-0206-R
Description
register to register
register to register-indirect
register-indirect to register
immediate data to register
code space to register
register to code space
data space to register
register to data space
register to register data
stack pop (source pre-
incremented)
register to register data
stack push (dest post-
decremented)
RAMY to register, indirect
register to RAMY, indirect
register to register, direct,
16-bit MOV
Bytes
3
3
3
3
3
3
3
3
3
3
3
3
3
Cycles
10
5
5
6
4
7
8
7
8
9
7
7
7
© 2006 Sensory Inc.
Waitstate
+Cycles/
4*
4*
3
3
3
3
4
4
3
3
3
3
3
Data Sheet