pt6105 China Resources Powtech (Shanghai) Co., Ltd, pt6105 Datasheet - Page 8

• Manufacturer Part Number: pt6105
• Description: Multi-cell Battery Management Front End With I 2 C Interface
• Manufacturer: China Resources Powtech (Shanghai) Co., Ltd

REGISTERS
Table 1. Registers
1. A "1" written to a configuration bit causes the action to be taken. A "1" read from a status
Table 2. Configuration Register (ADDR:00H)
China Resources Powtech (Shanghai) Limited
PT6105_DS Rev EN_1.1
BIT 7,6: Reserved for future expansion.
BIT 5: This bit control the chip operates in sleep mode or wake up mode.
BIT 4: This bit prevents or allows write the charge set registers(02H,04H).
BIT 3: This bit prevents or allows write the discharge set registers(03H).
BITS 2,1,0: The two bits decide the number of cells in 7 cells mode.
ADDR REGISTER
00H
ADDR REGISTER
0AH
0BH
0CH
0DH
bit indicates that the condition exists.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
0 = Sleep mode; (Default)
1 = Wake up mode.
0 = Prevent;(Default)
1 = Allow.
0 = Prevent;(Default)
1 = Allow.
000~011 = 3 cells;(Default)
1 0 0 = 4 cells;
1 0 1 = 5 cells;
1 1 0 = 6 cells;
1 1 1 = 7 cells.
Configuration and Status READ/WRITE Reserved Reserved
Configuration and Status
Operating Status
Cell Balance
DSC Set
Balance Current Set
ADC Data
Registers Writer Enable
READ/WRITE
READ/WRITE
READ/WRITE Reserved Reserved
READ/WRITE
READ/WRITE
READ/WRITE Reserved Reserved Reserved Reserved Reserved Reserved
READ/WRITE Reserved Reserved Reserved Reserved Reserved Reserved Reserved
READ
READ
7
Reserved Reserved Reserved
DSCD[7] DSCD[6] DSCD[5] DSCD[4] DSCD[3] DSCD[2] DSCD[1] DSCD[0]
C1VD[7]
C2VD[7]
C3VD[7]
C4VD[7]
C5VD[7]
C6VD[7]
C7VD[7]
ETMP[7]
CB7ON
DSCV2
WWW.CRPOWTECH.COM
7
0
0
0
0
0
0
0
0
0
6
C1VD[6]
C2VD[6]
C3VD[6]
C4VD[6]
C5VD[6]
C6VD[6]
C7VD[6]
ETMP[6]
CB6ON
DSCV1
6
0
0
0
0
0
0
0
0
0
WKUP
5
C1VD[5] C1VD[4] C1VD[3] C1VD[2] C1VD[1]
C2VD[5] C2VD[4] C2VD[3] C2VD[2] C2VD[1]
C3VD[5] C3VD[4] C3VD[3] C3VD[2] C3VD[1]
C4VD[5] C4VD[4] C4VD[3] C4VD[2] C4VD[1]
C5VD[5] C5VD[4] C5VD[3] C5VD[2] C5VD[1]
C6VD[5] C6VD[4] C6VD[3] C6VD[2] C6VD[1]
C7VD[5] C7VD[4] C7VD[3] C7VD[2] C7VD[1]
ETMP[5] ETMP[4] ETMP[3] ETMP[2] ETMP[1]
CB5ON
Multi-cell Battery Management
DSCV0
WKUP
5
0
0
0
0
0
0
0
0
0
Front End with I
CHSET DSSET CELLN2 CELLN1
4
CB4ON
CHSET
DSCT2
UVLO
4
0
0
0
0
0
0
0
0
0
3
ADCFAIL
CB3ON
DSSET
DSCT1
3
0
0
0
0
0
0
0
0
0
2
CELLN2
LDFAIL
CB2ON
DSCT0
2
0
0
0
0
0
0
0
0
0
PT6105
2
1
C Interface
C1VD[9]
C2VD[9]
C3VD[9]
C4VD[9]
C5VD[9]
C6VD[9]
C7VD[9]
DSCD[9] DSCD[8]
ETMP[9]
CELLN1
CB1ON
DSCEN
TSD
BC1
1
CELLN0
0
LDMONEN
Reserved
C1VD[0]
C1VD[8]
C2VD[0]
C2VD[8]
C3VD[0]
C3VD[8]
C4VD[0]
C4VD[8]
C5VD[0]
C5VD[8]
C6VD[0]
C6VD[8]
C7VD[0]
C7VD[8]
ETMP[0]
ETMP[8]
CELLN0
WR EN
DSC
BC0
0
Page 8