hcts646ms Intersil Corporation, hcts646ms Datasheet

no-image

hcts646ms

Manufacturer Part Number
hcts646ms
Description
Radiation Hardened Octal Bus Transceiver/register, Three-state
Manufacturer
Intersil Corporation
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Cosmic Ray Upset Rate 2 x 10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS646MS is a Radiation Hardened Three-
State Octal Bus Tranceiver/Register with Non-Inverting
outputs. This device is a bus transceiver with D-type flip-flops
which act as internal storage registers. Data on the A bus or
the B bus can be clocked into the registers on a High-to-Low
transition of either CAB ro CBA clock inputs. Output enable
(OE) and Direction (DIR) inputs control the transceiver func-
tions. Data present at the high impedance output can be
stored in either register or both but only one of the two buses
can be enabled as outputs at any one time. The select con-
trols (SAB and SBA) can multiplex stored and transparent
(real time) data. The direction control determines which data
bus will receive data when the OE pin is LOW. In the high
impedance mode (OE high), A data can be stored in one reg-
ister and B data in the other register. Data at the A or B termi-
nals can be clocked into the storage flip-flops at any time.
The HCTS646MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS646MS is supplied in a 24 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS646DMSR
HCTS646KMSR
HCTS646D/Sample
HCTS646K/Sample
HCTS646HMSR
Bit-Day (Typ)
- Bus Driver Outputs - 15 LSTTL Loads
- VIL = 0.8V Max
- VIH = VCC/2
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
|
Copyright
-9
TEMPERATURE RANGE
12
o
Errors/Bit Day
C to +125
©
RAD (Si)/s
-55
-55
Intersil Corporation 1999
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
Octal Bus Transceiver/Register, Three-State
706
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
GND
CAB
HCTS646MS
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
SCREENING LEVEL
FLATPACK PACKAGE (FLATPACK)
24 LEAD CERAMIC DUAL-IN-LINE
24 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
MIL-STD-1835 CDFP4-F24
MIL-STD-1835 CDIP2-T24
10
11
12
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
TOP VIEW
Radiation Hardened
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead SBDIP
24 Lead Ceramic Flatpack
Die
Spec Number
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
File Number
PACKAGE
VCC
CBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
518628
3074.1
VCC
CBA
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7

Related parts for hcts646ms

hcts646ms Summary of contents

Page 1

... The HCTS646MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS646MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...

Page 2

... HCTS646MS PINS TRUTH TABLE DATA I/O* SAB SBA A0 THRU A7 B0 THRU B7 ...

Page 3

... VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.8V (Note 2) NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS646MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCTS646MS GROUP (NOTES 1, 2) ...

Page 5

... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH IOZL/IOZH Specifications HCTS646MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT ...

Page 6

... Each pin except VCC and GND will have a resistor of 680 OPEN - NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS646MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS646MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS646MS AC Load Circuit TPHL TTHL 80% 20% UNITS 713 DUT TEST POINT 50pF RL = 500 Spec Number 518628 ...

Page 9

... Three-State High Timing Diagrams VIH INPUT VS VIL TPZH VOH VT OUTPUT VOZ THREE-STATE HIGH VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 3.60 GND 0 HCTS646MS Three-State Load Circuit TPLZ VW UNITS Three-State Load Circuit TPHZ VW UNITS 714 VCC RL TEST ...

Page 10

... A1 (5) A2 (6) A3 (7) A4 (8) A5 (9) NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS646 is TA14420A. HCTS646MS HCTS646MS DIR SAB CAB VCC CBA SBA (3) ...

Page 11

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HCTS646MS EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...

Related keywords