hcts02ms Intersil Corporation, hcts02ms Datasheet

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hcts02ms

Manufacturer Part Number
hcts02ms
Description
Radiation Hardened Quad 2-input Nor Gate
Manufacturer
Intersil Corporation
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD(Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS02MS is a Radiation Hardened Quad 2-Input
NOR Gate. A low on both inputs forces the output to a High state.
The HCTS02MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS02MS is supplied in a 14 lead Ceramic Flatpack Pack-
age (K suffix) or a 14 lead SBDIP Package (D suffix).
Ordering Information
HCTS02DMSR
HCTS02KMSR
HCTS02D/
Sample
HCTS02K/
Sample
HCTS02HMSR
(Typ)
- VIL = 0.8V Max
- VIH = VCC/2 Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD(Si)/s 20ns Pulse
5 A at VOL, VOH
|
o
o
Copyright
C
C
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
C to +125
LEVEL
©
Rads (Si)/s
Intersil Corporation 1999
o
-9
C
2
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
/mg
Errors/Bit-Day
PACKAGE
1
Pinouts
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
(2, 5, 8, 11)
(3, 6, 9, 12)
HCTS02MS
GND
A1
B1
A2
B2
Y1
Y2
An
Bn
An
H
H
L
L
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
MIL-STD-1835 CDFP3-F14
Y1
A1
B1
Y2
A2
B2
MIL-STD-1835 CDIP2-T14
Quad 2-Input NOR Gate
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Bn
H
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
Y4
B4
A4
Y3
B3
A3
OUTPUTS
Yn
(1, 4, 10, 13)
Yn
H
L
L
L
518841
2137.2
VCC
Y4
B4
A4
Y3
B3
A3

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hcts02ms Summary of contents

Page 1

... NOR Gate. A low on both inputs forces the output to a High state. The HCTS02MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS02MS is supplied lead Ceramic Flatpack Pack- age (K suffi lead SBDIP Package (D suffix). Ordering Information PART ...

Page 2

... Functional Test VIH = 2.25V, VIL = 0.8V, (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS02MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 3

... VCC = 4.5V TPLH VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = 3V. 3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS02MS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 ...

Page 4

... Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised. 2. Table 5 parameters only. CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. Specifications HCTS02MS GROUP B SUBGROUP 5 5 -15 Hour TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD 100% 5004 ...

Page 5

... Each pin except VCC and GND will have a resistor of 10K 2. Each Pin except VCC and GND will have a resistor of 1k OPEN 1, 4, 10, 13 NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS02MS 1/2 VCC = 3V 0.5V VCC = ...

Page 6

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS02MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 7

... INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL FIGURE 1 AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS02MS AC Load Circuit TPHL TTHL 80% 20% UNITS DUT TEST POINT 50pF RL = 500 FIGURE 2 Spec Number 518841 ...

Page 8

... Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 m x 100 mils Metallization Mask Layout A1 (2) B1 (3) Y2 (4) A2 (5) HCTS02MS HCTS02MS Y1 VCC Y4 (1) (14) (13) (6) (7) (8) B2 GND A3 8 (12) B4 (11) A4 (10) Y3 (9) B3 518841 Spec Number ...

Page 9

... Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. HCTS02MS D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C) c1 LEAD FINISH xxxxxxxxx ...

Page 10

... Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. HCTS02MS K14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE SYMBOL ...

Page 11

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 HCTS02MS EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...

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